Methods and Devices for Self-Interference Cancelation

ABSTRACT

A communication circuit arrangement includes a signal path circuit to estimate, using a first kernel dimension filter and a first delay tap dimension filter, a first interference signal produced by a first amplifier. The signal path circuit further estimates, using a second kernel dimension filter and a second delay tap dimension filter, a second interference signal produced by a second amplifier. A cancellation circuit of the communication circuit arrangement may subtract a combination of the first interference signal and the second interference signal from a received signal to obtain a filtered signal, and one or more filter adaptation circuits may alternate between a kernel update phase and a delay update phase to update the first kernel dimension filter and the second kernel dimension filter during the kernel update phase, and update the first delay tap dimension filter and the second delay tap dimension filter during the delay update phase.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national stage entry according to 35 U.S.C. 371 ofPCT Application No. PCT/US2016/054286 filed on Sep. 29, 2016, whichclaims priority to U.S. application Ser. No. 15/214,531 filed on Jul.20, 2016, which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

Various embodiments relate generally to methods and devices forself-interference cancelation.

BACKGROUND

Interference cancelation is an important component of radiocommunication systems, in particular for self-interference cancelationfor multi-radio coexistence, frequency division duplexing, andfull-duplex radio communication systems. As such radio communicationsystems may transmit and receive simultaneously, interference may leakfrom the transmit chain to the receive chain and consequently producecorruptive self-interference signal in signals received at the receivedchain. While certain largely ‘passive’ solutions such as specialduplexing circuitry may be effective in sufficiently isolating thereceive chain from the transmit chain, these solutions may be expensiveand thus undesirable for many manufacturers.

Digital self-interference cancelation may thus offer a lower costalternative solution. In such self-interference cancelation solutions,one or more adaptive filters may be utilized to model the leakage pathfrom the transmit chain to the receive chain. Accordingly, assuming anaccurate model the adaptive filters may be able to produce estimatedinterference signals from original transmit signals. The receive chainmay then subtract these estimated interference signals from receivedsignals, thus canceling the self-interference from the received signalsand producing a clean signal that may be largely free of residualself-interference.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts throughout the different views. The drawings are not necessarilyto scale, emphasis instead generally being placed upon illustrating theprinciples of the invention. In the following description, variousembodiments of the invention are described with reference to thefollowing drawings, in which:

FIG. 1 shows a diagram of communication circuitry;

FIG. 2 shows a flow chart illustrating a self-cancelation interferenceprocedure;

FIG. 3 shows a flow chart illustrating update of a kernel dimensionfilter;

FIG. 4 shows a flow chart illustrating update of a delay tap dimensionfilter;

FIG. 5 shows a graphical depiction of a matrix storage scheme;

FIG. 6 shows a diagram of processing circuitry including a signal pathand an adaptation engine;

FIG. 7A-7B show a decoupled kernel dimension input signal calculationand decoupled delay tap dimension input signal calculation;

FIG. 8 shows a resource table and hardware pipeline clock schedule;

FIG. 9 shows a diagram of a decoupled kernel dimension input signalcalculation circuit;

FIG. 10 shows a diagram of a decoupled delay tap dimension input signalcalculation circuit;

FIG. 11 shows diagrams of a correlation and cross-correlation updatecircuit;

FIG. 12 shows a matrix memory indexing scheme;

FIG. 13 shows a diagram of a DCD circuit;

FIG. 14 shows a diagram of a maximum cross-correlation identificationcircuit;

FIG. 15 shows a diagram of a memory-based power amplifier estimation;

FIG. 16 shows a first method of performing interference cancelation;

FIG. 17 shows a second method of performing interference cancelation;

FIG. 18 shows a diagram of a bilinear interference cancelation systemfor a MIMO architecture;

FIG. 19 shows a diagram illustrating adaptation resource sharing for aMIMO architecture;

FIG. 20 shows a diagram of a bilinear interference cancelationarchitecture for MIMO with joint FIR filter estimation;

FIG. 21 shows a third method of performing interference cancelation; and

FIG. 22 shows a fourth method of performing interference cancelation.

DESCRIPTION

The following detailed description refers to the accompanying drawingsthat show, by way of illustration, specific details and embodiments inwhich the invention may be practiced.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration”. Any embodiment or design described herein as“exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs.

The words “plurality” and “multiple” in the description and the claimsexpressly refer to a quantity greater than one. The terms “group (of)”,“set [of]”, “collection (of)”, “series (of)”, “sequence (of)”, “grouping(of)”, etc., and the like in the description and in the claims, if any,refer to a quantity equal to or greater than one, i.e. one or more. Anyterm expressed in plural form that does not expressly state “plurality”or “multiple” refers to a quantity equal to or greater than one. Theterms “proper subset”, “reduced subset”, and “lesser subset” refer to asubset of a set that is not equal to the set, i.e. a subset of a setthat contains less elements than the set.

It is appreciated that any vector and/or matrix notation utilized hereinis exemplary in nature and is employed solely for purposes ofexplanation. Accordingly, it is understood that the approaches detailedin this disclosure are not limited to being implemented solely usingvectors and/or matrices, and that the associated processes andcomputations may be equivalently performed with respect to sets,sequences, groups, etc., of data, observations, information, signals,samples, symbols, elements, etc. Furthermore, it is appreciated thatreferences to a “vector” may refer to a vector of any size ororientation, e.g. including a 1×1 vector (e.g. a scalar), a 1×M vector(e.g. a row vector), and an M×1 vector (e.g. a column vector).Similarly, it is appreciated that references to a “matrix” may refer tomatrix of any size or orientation, e.g. including a 1×1 matrix (e.g. ascalar), a 1×M matrix (e.g. a row vector), and an M×1 matrix (e.g. acolumn vector).

A “circuit” as used herein is understood as any kind oflogic-implementing entity, which may include special-purpose hardware ora processor executing software. A circuit may thus be an analog circuit,digital circuit, mixed-signal circuit, logic circuit, processor,microprocessor, Central Processing Unit (CPU), Graphics Processing Unit(GPU), Digital Signal Processor (DSP), Field Programmable Gate Array(FPGA), integrated circuit, Application Specific Integrated Circuit(ASIC), etc., or any combination thereof. Any other kind ofimplementation of the respective functions which will be described belowin further detail may also be understood as a “circuit”. It isunderstood that any two (or more) of the circuits detailed herein may berealized as a single circuit with substantially equivalentfunctionality, and conversely that any single circuit detailed hereinmay be realized as two (or more) separate circuits with substantiallyequivalent functionality. Additionally, references to a “circuit” mayrefer to two or more circuits that collectively form a single circuit.The term “circuit arrangement” may refer to a single circuit, acollection of circuits, and/or an electronic device composed of one ormore circuits.

As used herein, “memory” may be understood as a non-transitorycomputer-readable medium in which data or information can be stored forretrieval. References to “memory” included herein may thus be understoodas referring to volatile or non-volatile memory, including random accessmemory (RAM), read-only memory (ROM), flash memory, solid-state storage,magnetic tape, hard disk drive, optical drive, etc., or any combinationthereof. Furthermore, it is appreciated that registers, shift registers,processor registers, data buffers, etc., are also embraced herein by theterm memory. It is appreciated that a single component referred to as“memory” or “a memory” may be composed of more than one different typeof memory, and thus may refer to a collective component comprising oneor more types of memory. It is readily understood that any single memorycomponent may be separated into multiple collectively equivalent memorycomponents, and vice versa. Furthermore, while memory may be depicted asseparate from one or more other components (such as in the drawings), itis understood that memory may be integrated within another component,such as on a common integrated chip.

The term “base station” used in reference to an access point of a mobilecommunication network may be understood as a macro base station, microbase station, Node B, evolved NodeB (eNB), Home eNodeB, Remote RadioHead (RRH), relay point, etc. As used herein, a “cell” in the context oftelecommunications may be understood as a sector served by a basestation. Accordingly, a cell may be a set of geographically co-locatedantennas that correspond to a particular sectorization of a basestation. A base station may thus serve one or more cells (or sectors),where each cell is characterized by a distinct communication channel.Furthermore, the term “cell” may be utilized to refer to any of amacrocell, microcell, femtocell, picocell, etc.

For purposes of this disclosure, radio communication technologies may beclassified as one of a Short Range radio communication technology,Metropolitan Area System radio communication technology, or CellularWide Area radio communication technology. Short Range radiocommunication technologies include Bluetooth, WLAN (e.g. according toany IEEE 802.11 standard), and other similar radio communicationtechnologies. Metropolitan Area System radio communication technologiesinclude Worldwide Interoperability for Microwave Access (WiMax) (e.g.according to an IEEE 802.16 radio communication standard, e.g. WiMaxfixed or WiMax mobile) and other similar radio communicationtechnologies. Cellular Wide Area radio communication technologiesinclude Global System for Mobile Communications (GSM), Code DivisionMultiple Access 2000 (CDMA2000), Universal Mobile TelecommunicationsSystem (UMTS), Long Term Evolution (LTE), General Packet Radio Service(GPRS), Evolution-Data Optimized (EV-DO), Enhanced Data Rates for GSMEvolution (EDGE), High Speed Packet Access (HSPA), etc., and othersimilar radio communication technologies. Cellular Wide Area radiocommunication technologies also include “small cells” of suchtechnologies, such as microcells, femtocells, and picocells. CellularWide Area radio communication technologies may be generally referred toherein as “cellular” communication technologies. It is understood thatexemplary scenarios detailed herein are demonstrative in nature, andaccordingly may be similarly applied to various other mobilecommunication technologies, both existing and not yet formulated,particularly in cases where such mobile communication technologies sharesimilar features as disclosed regarding the following examples.

The term “network” as utilized herein, e.g. in reference to acommunication network such as a mobile communication network,encompasses both an access section of a network (e.g. a radio accessnetwork (RAN) section) and a core section of a network (e.g. a corenetwork section). The term “radio idle mode” or “radio idle state” usedherein in reference to a mobile terminal refers to a radio control statein which the mobile terminal is not allocated at least one dedicatedcommunication channel of a mobile communication network. The term “radioconnected mode” or “radio connected state” used in reference to a mobileterminal refers to a radio control state in which the mobile terminal isallocated at least one dedicated uplink communication channel of amobile communication network.

Unless explicitly specified, the term “transmit” encompasses both direct(point-to-point) and indirect transmission (via one or more intermediarypoints). Similarly, the term “receive” encompasses both direct andindirect reception. The term “communicate” encompasses one or both oftransmitting and receiving, i.e. unidirectional or bidirectionalcommunication in one or both of the incoming and outgoing directions.The term “calculate” encompass both ‘direct’ calculations via amathematical expression/formula/relationship and ‘indirect’ calculationsvia lookup tables and other array indexing or searching operations.

Radio communication systems that involve simultaneous transmission andreception, including frequency-division duplexing, full duplexing, andmulti-radio coexistence, commonly suffer from self-interference that iscaused by a device's own transmitter. As both frequency-division andfull duplexing devices transmit and receive simultaneously, suchself-interference arises when the transmit signal leaks onto the receivepath in the transceiver. Due to the fact that transmit power isconsiderably higher than receive power, the transmit signal may dominatethe received signals and thus lead to a high degree of corruption at thereceiver.

The transmit signal involved in self-interference may conventionallyleak from the transmit path to the receive path either through aduplexer and/or over the air. While duplexer leakage may be prevented inthrough specialized duplexing circuitry such components generally needto be very expensive circuitry in order to provide isolation that issufficient to avoid crippling self-interference.

Self-interference cancelation has thus been recognized as a potentiallymore cost-effective solution. In self-interference cancelation schemes,adaptive filters may be used to ‘model’ the transmit path leakage inorder to generate estimated interference signals. These estimatedinterference signals may then be provided to the receive path, which maysubtract the estimated interference signal from the received signal.Depending on the accuracy of the employed adaptive filters, the receivermay be able to counter the leakage signal and thus produce a cleansignal that is largely free of interference. Self-interferencecancelation may thus relax the requirements for expensive duplexers andallow for most cost-efficient transceiver designs.

The adaptive filters used in self-interference cancelation techniquesmay aim to model the radio power amplifier employed in the transmitpath. However, as such radio power amplifiers are generally non-linear,the approximation techniques required to generate accurate filterweights may be relatively complex. Accordingly, many self-interferencecancelation approaches may model the power amplifier as a set of‘kernels’, where each kernel is tailored to model a separate nonlinearcomponent of the response of power amplifier response. Theself-interference cancelation architecture may then derive a separateadaptive filter tailored to each kernel, where the each input sample forthe power amplifier may be decomposed into a kernel sample for eachkernel and applied to the corresponding adaptive filter. As such designsmay conventionally utilize memory-based filters, each adaptive filtermay be applied to each kernel sample in addition to the previous kernelsamples, or ‘taps’, in order to generate a filter output. The sum of theadaptive filter output for each kernel may then give the estimatedinterference signal (where each adaptive filter models the interferencecontributed by the corresponding kernel), which may be subtracted fromthe received signal in order to provide a ‘clean’ signal that isconceivably free of self-interference.

The adaptation engine responsible for dynamically updating the adaptivefilter weights may play a critical role in effective self-interferencecancelation. These adaptation engines may predominantly examine the‘clean’ signal in order to evaluate the effectiveness of theinterference cancelation, i.e. whether there is any interference residueremaining in the clean signal after the estimated interference signalhas been removed. Based on the efficacy of the interference cancelation,the adaptation engines may provide updates to the adaptive filterweights in order to continuously improve the cancelation performance.

Many adaptation schemes have been developed that offer varying tradeoffsbetween convergence and area/power. Accordingly, while approaches suchas Recursive Least Squares (RLS) designs may offer extremely fastconvergence at the expense of large area and power requirements forhardware implementations. Conversely, Least Mean Squares (LMS) may offercomparatively small area and power costs while suffering from poorconvergence speed. Various other adaptation schemes and accompanyinghardware designs have been proposed that similarly provide differentconvergence to area and power tradeoffs.

Many existing adaptation solutions may jointly update filter weights fora two-dimensional filter over both kernels and taps, i.e. by consideringthe PA response as varying over both taps and kernels. As previouslyindicated, power amplifier input signals may be decomposed into kernelsamples according each of a set of predetermined kernels thatcollectively model the power amplifier. Each of the adaptive filters maythen be tailored to estimate the interference associated with arespective kernel based on the current kernel sample and a number ofpast kernel samples. The adaptive filters may thus function as FiniteImpulse Response (FIR) filters that hold the current and multipleprevious input samples, apply a respective filter weight to each inputsample, and sum the weighted outputs to obtain the filter output.Accordingly, for a given memory length M, i.e. M total taps, eachadaptive filter may apply a respective filter weight (out of M totalfilter weights) to a respective one of the M taps. Expressedmathematically, given an length-M input sample vector X(t)=[X_(t),X_(t−1), X_(t−2), . . . , X_(t−M+1)] at a given time t, an FIR filter Wwith M×1 weight vector W=[w₀, w₁, . . . , w_(M−1)]^(T) may calculate afilter output e(t) as

$\begin{matrix}\begin{matrix}{{e(t)} = {{X(t)}W}} \\{= {{w_{0}X_{t}} + {w_{1}X_{t - 1}} + {w_{2}X_{t - 2}} + \ldots + {w_{M - 1}X_{t - M + 1}}}}\end{matrix} & (1)\end{matrix}$

where X_(t) is the current input sample and X_(t−1) to X_(t−M+1) are theM−1 previous input samples and each of w₀ to W_(M−1) is a complexweight.

Accordingly, the adaptive filter may need to store the M−1 previousinput samples of X(t) in addition to the current sample and, for eachnew input sample, apply the M weights of W to X(t) in order to obtainfilter output e(t), which may represent the estimated self-interference,or ‘echo’. By selecting proper weights, the FIR filter W may be able to‘filter’ X(t) in order to produce filter output y(t) with certaindesired characteristics, such as e.g. to approximate the kernel outputin the context of self-interference cancelation.

As previously detailed, many self-interference cancelation schemes mayemploy kernelization to model the power amplifier as a set of kernelsthat each represent a non-linear component of the power amplifier (wherethe case described above regarding Equation (1) may thus be anon-kernelized or single kernel approach). Accordingly, suchself-interference cancelation designs may employ a dedicated adaptivefilter for each kernel, where each adaptive filter estimates theself-interference resulting from each respectively assigned kernel.Accordingly, the overall filter may be composed of multiple kernelfilters that each model a respective kernel. In other words, for a modelusing K kernels and M taps, the filter W may be a K×M matrix where eachrow of W may contain the M weights for a respective kernel filter.Accordingly, W may be of the form

$\begin{matrix}{W = \begin{bmatrix}w_{t}^{(1)} & w_{t - 1}^{(1)} & \ldots & w_{t - M + 1}^{(1)} \\ \vdots & \vdots & \ddots & \vdots \\w_{t}^{(K)} & w_{t - 1}^{(K)} & \ldots & w_{t - M + 1}^{(K)}\end{bmatrix}} & (2)\end{matrix}$

where each k-th row for k=1, 2, . . . , K contains the M filter weightsfor samples X_(t) ^((k)), X_(t−1) ^((k)), . . . , X_(t−M+1) ^((k)) ofthe k-th kernel.

The filter system may thus need to retain the previous M samples foreach kernel (including the current sample); accordingly, X(t) may thusbe defined as a K×M matrix of the past M samples for each of the Kkernels, i.e.

$\begin{matrix}{{X(t)} = \begin{bmatrix}X_{t}^{(1)} & X_{t - 1}^{(1)} & \ldots & X_{t - M + 1}^{(1)} \\ \vdots & \vdots & \ddots & \vdots \\X_{t}^{(K)} & X_{t - 1}^{(K)} & \ldots & X_{t - M + 1}^{(K)}\end{bmatrix}} & (3)\end{matrix}$

Denoting the kernel samples for the k-th kernel as X^((k))(t)=[X_(t)^((k)) . . . X_(t−M+1) ^((k))] and the kernel weights for the k-thkernel as W_((k))=[w_(t) ^((k)) . . . w_(t−M+1) ^((k))], the overallfilter output e(t) may be given as

$\begin{matrix}{{e(t)} = {\sum\limits_{i = 1}^{K}{{X^{(i)}(t)}W^{(i)}}}} & (4)\end{matrix}$

The filter output may thus produce a single symbol e(t) at each time tthat estimates the self-interference as the sum of the application ofeach of the K kernel filters to the previous M kernel samples of eachkernel. Accordingly, such self-interference cancelation designs (whichmay be commonly known as “Hammerstein” models) may model the leakage asthe sum of the contributions of each kernel. The estimated interferencesignal e (t) may then be subtracted from the received signal y(t)(observed at the receive chain). Assuming the filter W is a suitableapproximation of the actual self-interference signal, the resulting‘clean’ signal z(t) (where z(t)=y(t)−e(t)) may only contain a small oreven negligible amount of residual self-interference and thus may beproperly received and decoded by the receiver.

Self-interference cancelation designs may generally compute filterweight updates based on analysis of the clean signal z(t) to determineboth which filter weights of W are contributing to the interferenceresidue in z(t) and how to optimally adapt these filter weights tominimize the interference residue for future input samples. As theoverall filter W in such conventional solutions may be a K×M matrix offilter weights, an optimal self-interference cancelation scheme mayadapt all of the KM total filter weights at each input sample. However,the required computational complexity of updating all KM filter weightsmay be prohibitively high and, consequently, many self-interferencecancelation schemes have explored adaptation schemes that both reducethe number of weights updated at each stage and reduce the computationalcomplexity of the update calculation.

As detailed herein, an advantageous self-interference cancelationsolution of this disclosure may ‘decouple’ the FIR dimension from thekernel dimension in order to allow for computationally manageableadaptation stages. As will be detailed, this decoupling may allow forthe FIR dimension to be updated separately from the kernel dimension andmay additionally enable the usage of numerous additional computationaltechniques that may reduce the adaptation complexity. In particular forhardware implementations, the adaptation engine of this disclosure mayprovide substantial reductions in area and power and may thus prove tobe an attractive design feasible with current radio technology.Additionally, the self-interference cancelation scheme may offerconfigurability, and accordingly may be able to support variable numbersof taps and kernels for the filter weights.

FIG. 1 shows a block diagram of communication circuitry 100, which mayimplement the self-interference cancelation system of this disclosureand may be a radio communication device (e.g. a mobile terminal, basestation, network access point, etc.). As shown in FIG. 1 , signal source102 may generate a baseband transmit signal s(t) for power amplifier104, which power amplifier 104 may amplify (following radio modulation,analog-to-digital conversion, and other pre-amplification stages notexplicitly shown in FIG. 1 ) to produce an amplified RF transmit signal.Power amplifier 104 may provide the amplified RF transmit signal toduplexer 106, which may be placed between power amplifier 104 andreceiver 110 in order to allow for power amplifier 104 and receiver 110to share antenna 108 (which may be a single antenna or an antennaarray). Accordingly, in a full-duplex or frequency-division duplexingscheme duplexer 106 may allow power amplifier 104 and receiver 110 tosimultaneously transmit and receive, respectively, with antenna 108.Without loss of generality, communication circuitry 100 may be employedin short range, metropolitan, or cellular radio communicationtechnologies such as 3GPP technologies (LTE, UMTS, GSM, etc.), WiFi,Bluetooth, etc. Communication circuitry 100 may be included in eitheruplink or downlink devices, including mobile terminals, base station,and network access points.

In addition to duplexer leakage, transmissions may leak onto the receivechain through the air, e.g. even if no antennas are shared (notexplicitly shown in FIG. 1 ). Accordingly, one or both of the shared useof antenna 108 and wireless leakage may create self-interference thatleaks from power amplifier 104 to receiver 110 over leakage path 130 asshown in FIG. 1 (where leakage path 130 may be composed of a wiredand/or wireless path). Accordingly, the amplified radio transmit signalproduced by power amplifier 104 via amplification of baseband transmitsignal s(t) may appear in the received baseband signal y(t) produced byreceiver 110. Accordingly, the presence of this leakage signal in y(t)may corrupt a desired component of y(t), i.e. the signal actuallytargeted by receiver 110 (such as a downlink signal received from a basestation or an uplink signal received from a mobile terminal).

While incorporation of specialized duplexing circuitry in duplexer 106may minimize the self-interference, such may be considerably expensiveand thus undesirable in many designs. In order to enable sufficientreception performance by receiver 110, communication circuitry 100 mayinstead implement the self-interference cancelation of this disclosurewith cancelation circuitry 112. As will be detailed, cancelationcircuitry 112 may be configured to generate an estimated interferencesignal e(t) from s(t) and subtract e(t) from y(t) to produce cleansignal z(t). Assuming generation of e(t) that accurately models leakagepath 130, cancelation circuitry 112 may be able to effectively removethe self-interference signal from y(t) and thus produce clean signalz(t) that is largely free of self-interference. Cancelation circuitry112 may employ an adaptive filter system in order to model leakage path130 which, as detailed below, decouples the PA dimension of the filterfrom the FIR dimension, thus allowing for reduced computational demandsduring adaptation.

As will be detailed, in an aspect of this disclosure communicationcircuitry 100 may be characterized as a communication circuitarrangement including a signal path circuit (e.g. the signal path ofcancelation circuitry 112) configured to separately apply a kerneldimension filter and a delay tap dimension filter to an input signal foran amplifier to obtain an estimated interference signal, a cancelationcircuit (e.g. cancelation circuit 122) configured to subtract theestimated interference signal from a received signal to obtain a cleansignal, and a filter update circuit (e.g. the adaptation engine ofcancelation circuitry 112) configured to alternate between updating thekernel dimension filter and the delay tap dimension filter. In anotheraspect of this disclosure, communication circuitry 100 may becharacterized as a communication circuit arrangement including asubsignal generation circuit (e.g. kernel generation circuit 114)configured to obtain one or more subsignals from an input signal for anamplifier, each of the one or more subsignals representing a non-linearcomponent of an amplifier response and composed of a plurality of delaytaps, a signal path circuit (e.g. the signal path of cancelationcircuitry 112) configured to separately apply a first filter and asecond filter to the one or more subsignals to obtain an estimatedinterference signal, wherein the first filter approximates the amplifierresponse over the one or more subsignals and the second filterapproximates the amplifier response over the plurality of delay taps, acancelation circuit (e.g. cancelation circuit 122) configured tosubtract the estimated interference signal from the received signal toobtain a clean signal, and a filter update circuit (e.g. the adaptationengine of cancelation circuitry 112) configured to alternate betweenupdating the first filter and updating the second filter using the cleansignal.

Accordingly, as opposed to utilizing a two-dimensional filter W asexpressed above in Equation (2), cancelation circuitry 112 may utilize asingle-dimensional K×1 power amplifier filter W_(PA) (PA filter circuit118) and a single-dimensional M×1 FIR filter W_(F) (FIR filter circuit120). Instead of employing M different weights for each of the K PAkernels, cancelation circuitry 112 may thus decouple the PA dimensionfrom the FIR dimension and utilize a single set of K×1 PA filter weightsin W_(PA) to collectively model the K PA kernels (over all taps) andsimilarly utilize a single set of M×1 FIR filter weights in W_(F) tocollectively model the M taps (over all kernels). Given this drasticreduction in the amount of filter weights (from KM to K+M), cancelationcircuitry 112 may considerably reduce the amount of computation neededto adapt the filter weights. Accordingly, cancelation circuitry 112 maypresent an attractive self-interference cancelation system that offersstrong convergence speeds while avoiding excessively complex adaptationcalculations. Hardware area may consequently also be substantiallyreduced due to the lower computational complexity.

As shown in FIG. 1 , cancelation circuitry 112 may include kernelgeneration circuit 114, matrix memory 116, PA filter circuit 118, FIRfilter circuit 120, cancelation circuit 122, PA filter adaptationcircuit 124, FIR filter adaptation circuit 126, and adaptation switchcircuit 128. The corresponding functionality of the components ofcancelation circuitry 112 may be structurally realized/embodied ashardware logic, e.g. as one or more integrated circuits or FPGAs, assoftware logic, e.g. as one or more processors executing program codethat defining arithmetic, control, and I/O instructions stored in anon-transitory computer-readable storage medium, or as a combination ofhardware and software logic. Accordingly, while the individualcomponents of cancelation circuitry 112 are depicted separately in FIG.1 , this depiction serves to highlight the operation of cancelationcircuitry 112 on a functional level; consequently, one or more of thecomponents of cancelation circuitry 112 may be integrated into a commonhardware and/or software element. Additionally, the functionality ofcancelation circuitry 112 detailed herein (in particular e.g. theformulas/equations, flow charts, and prose descriptions) may be readilyincorporated by skilled persons into program code for retrieval from anon-transitory computer readable medium and execution by a processor.

Cancelation circuitry 112 may be logically divided into a signal pathand an adaptation engine, where the signal path may be tasked withgenerating the estimated interference signal e (t) and the adaptationengine may be tasked with adapting the filter coefficients of PA filtercircuit 118 and FIR filter circuit 120. Accordingly, the signal path maybe composed of kernel generation circuit 114, matrix memory 116, PAfilter circuit 118, FIR filter circuit 120, and cancelation circuit 122while the adaptation engine may be composed of PA filter adaptationcircuit 124, FIR filter adaptation circuit 126, and adaptation switch128. Accordingly, the signal path may derive the kernel signalsX_(t:t−M+1) ^((k)) for each kernel k for each input sample s(t) andapply PA filter W_(PA) to the kernel signals X_(t:t−M+1) ^((k)) for eachkernel k, thus producing a 1×M output vector (W_(PA) ^(T)X(t)), beforeapplying FIR filter W_(F) to W_(PA) ^(T)X(t) (yielding W_(PA)^(T)X(t)W_(F)) to obtain the estimated interference samples e(t). Thesignal path may thus produce a sample of e(t) for each input sample ofs(t) using the most recent M samples for each of the K kernels.

More specifically, kernel generation circuit 114 may obtain basebandtransmit signal s(t) from the receive path at the input to poweramplifier 104. Depending on the deployment of cancelation circuitry 112,signal source 102 may be a baseband modem or similar baseband processingcircuit (e.g. in a mobile terminal implementation) or a baseband unit(BBU) or similar baseband processing circuit (e.g. in a base station oraccess point implementation. Accordingly, kernel generation circuit 114may tap the input to PA 104 to obtain s(t) and may subsequently applyprocessing in order to derive the kernel samples X_(t) ^((1:K)), i.e.the most recent kernel sample for each of the K kernels. As previouslynoted, kernel generation circuit 114 circuit may rely on a ‘kernelized’model of PA 104 that estimates the non-linear response of PA 104 bydividing the response into multiple components, i.e. kernels, thatcollectively sum to model the overall response of PA 104. Such mayinclude using e.g. Cholesky decomposition or similar establishedprocessing solution in order to derive X_(t) ^((1:K)). Accordingly,kernel generation circuit 114 may be responsible for generating kernelsamples X_(t) ^((1:K)) from (t). Various such kernelization techniquesare established and are compatible for implementation in kernelgeneration circuit 114.

Kernel generation circuit 114 may thus generate kernel samples X_(t)^((1:K)) for each sample s(t) and provide the resulting samples X_(t)^((1:K)) to matrix memory 116. As previously detailed, cancelationcircuitry 112 may estimate the self-interference signal e(t) based onthe M most recent samples (including the current sample at time t) ofeach of the K kernels, i.e. X_(t:t−M+1) ^((k)). Accordingly, memorymatrix 116 may store the K×M matrix containing the M most recent samplesfor each of the K kernels, which may be expressed as X(t) as defined inEquation (3) at each time t.

As processing circuitry 118 may generate an estimated self-interferencesample e(t) at each time t, matrix memory 116 may update X(t) with the Knew kernel samples X_(t) ^((1:K)) for each time t and provide X(t) to PAfilter circuit 118. PA filter circuit 118 may store the K filter weightsof K×1 PA filter weight vector W_(PA), which may be expressed as

$\begin{matrix}{W_{PA} = \begin{bmatrix}w_{{PA},1} \\w_{{PA},2} \\ \vdots \\w_{{PA},K}\end{bmatrix}} & (5)\end{matrix}$

where each W_(PA,k), k=1, . . . , K is the complex PA weightcorresponding to the k-th PA kernel.

PA filter circuit 118 may then apply W_(PA) to X(t) as W_(PA) ^(T)X(t)to obtain an M×1 vector, which PA filter circuit 118 may provide to FIRfilter circuit 120. FIR filter circuit 120 may likewise store the Mfilter weights of M×1 filter weight vector W_(F), which may be expressedas

$\begin{matrix}{W_{F} = \begin{bmatrix}w_{F,1} \\w_{F,2} \\ \vdots \\w_{F,M}\end{bmatrix}} & (6)\end{matrix}$

where each w_(F,m), m=M is the complex FIR weight corresponding to them-th tap, i.e. the m-th most recent sample. As leakage path 130 mayinclude (in addition to the non-linear response of PA 104) multipletransmit and receive FIR filters, the weights of FIR filter W_(F) maytherefore model the various taps of each of these FIR filters.

FIR filter circuit 120 may then apply W_(F) to the output vector W_(PA)^(T)X(t) of PA filter circuit 118 as W_(PA) ^(T)X(t)W_(F) to obtain asingle estimated self-interference sample e(t) for each time t.Cancelation circuit 122 may then subtract e(t) from y(t) provided byreceiver 110 to obtain clean signal z(t)=y(t)−e(t) for each time t,which may be largely free of self-interference if e (t) closely matchesthe actual self-interference signal leaking from power amplifier 104through duplexer 106 on leakage path 130.

The efficacy of the self-interference cancelation scheme applied bycancelation circuitry 112 may depend on how accurately W_(PA) and W_(F)model the self-interference over each kernel and tap. Accordingly,cancelation circuitry 112 may employ the adaptation engine composed ofPA filter adaptation circuit 124, FIR filter adaptation circuit 126, andadaptation switch circuit 128 in order to dynamically update the filterweights W_(PA) and W_(F) of PA filter circuit 118 and FIR filter circuit120.

As the PA and FIR filter weights W_(PA) and W_(F) have been decoupled(compared to the ‘coupled’ weights of W in Equation (2)), the adaptationengine of cancelation circuitry 112 may be able to update W_(PA) andW_(F) separately, which may substantially reduce the computationalcomplexity of the update process and consequently reduce hardware areaand power requirements. Whereas update of the full K×M matrix W involvedconsidering all KM filter weights for update, the adaptation engine mayonly need to consider either K or M total filter weights of W_(PA) andW_(F), respectively, at a time. Additionally, the adaptation engine ofcancelation circuitry 112 may employ an adaptation scheme in whichW_(PA) or W_(F) (depending on which is currently being updated and whichis fixed) is updated for every input sample s(t). Accordingly, W_(PA) orW_(F) may continuously ‘track’ the system in real-time in order toadaptively track changes. Furthermore, such may provide the possibilityto re-use shared processing circuitry to update W_(PA) and W_(F) atdisparate times, thus allowing for further hardware reductions.

FIG. 2 shows method 200 illustrating the general procedure ofcancelation circuitry 112, which may iterate over each time t startingat 202. Kernel generation circuit 114 and matrix memory 116 may firstgenerate the KM entries of X(t) from s(t) based on the most recentkernel samples X_(t) ^((1:K)) and the past kernel samples X_(t−1:t−M+1)^((1:K)) in 204. Each set of kernel samples X_(t:t−M+1) ^((k)) may thusbe considered a ‘subsignal’ derived from baseband input signal s(t),e.g. according to kernel generation scheme such as based on Choleskydecomposition. PA filter circuit 118 and FIR filter circuit 120 may thenapply W_(PA) and W_(F), respectively, to X(t) as W_(PA) ^(T)X(t)W_(F) toobtain e(t) in 206. Cancelation circuit 122 may then subtract e(t) fromreceived signal y(t) to obtain clean signal z(t) in 208. If switchingcircuit 128 has currently selected W_(PA) for adaptation, PA filteradaptation circuit 124 may update W_(PA) based on z(t) and X(t) in 212,i.e. by evaluating the uncanceled leakage in z(t) resulting from X(t);alternatively, if switching circuit 128 has currently selected W_(F) foradaptation, FIR filter adaptation circuit 126 may update W_(F) based onz(t) and X(t) in 214. Method 200 may then iteratively repeat for t=t+1,where switching circuit 128 may periodically change the selectionbetween PA adaptation circuit 124 and FIR adaptation circuit 126 inorder to ensure that both W_(PA) and W_(F) are updated over time.

The decoupling of W_(PA) and W_(F) updates may provide considerablereductions in computational complexity due to the reduced number offilter weights, which may also open up the possibility for re-using thesame shared processing circuitry to update W_(PA) and W_(F) atalternating times (thus further saving hardware area). Additionally, thedecoupling of W_(PA) and W_(F) may allow for cancelation circuitry 112to also employ numerous additional computational techniques that furtherreduce the computational complexity. As will be further detailed below,such techniques may include a Dichotomous Coordinate Descent (DCD)update algorithm, simplified maximum magnitude selection, reduced matrixmemory storage, preprocessing calculation stages, and clock pipeliningschedules. The self-interference cancelation solution of this disclosuremay additionally offer configurability in terms of the supported numberof taps M and kernels K. Such enhancements are considered optional andmay or may not be included in various aspects of this disclosure.

The general update procedure of the adaptation engine of cancelationcircuitry 112 will first be detailed. As W_(PA) and W_(F) are decoupledinto two separate vectors, the adaptation engine may update each ofW_(PA) and W_(F) separately (as in 212 and 214 of method 200 dependingon the selection of switching circuit 128). By updating only one ofW_(PA) or W_(F) at a time, the adaptation engine may ‘fix’ one dimension(i.e. either the PA dimension or the FIR dimension) and ignore anydependencies on the fixed dimension during update of the otherdimension, thus simplifying the adaptation process. Accordingly,switching circuit 128 may control PA filter adaptation circuit 124 andFIR filter adaptation circuit 126 to alternate between updating the PAweights of W_(PA) and the FIR weights of W_(F). Accordingly, only K or Mfilter weights will be considered for update at a given time (resultingdirectly from the decoupling), which may present a drastic reductionover the KM filter weights of W.

As previously indicated, the adaptation engine may utilize clean signalz(t) in order to decide which filter weights to update. Morespecifically, as shown in FIG. 1 both PA filter adaptation circuit 124and FIR adaptation circuit 126 may receive both z(t) and X(t) (the cleansignal sample z(t) and kernel sample matrix X(t) at time t) and comparez(t) with X(t) to determine if z(t) is correlated with X(t).Accordingly, if z(t) is correlated with X(t), this may indicate that theself-interference cancelation is not effective and that the filterweights need to be adjusted to obtain more accurate estimates in e(t).Depending on the specifics of the adaptation scheme used by theadaptation engine, PA filter adaptation circuit 124 and FIR adaptationcircuit 126 may then analyze the relationship between z(t) with X(t) inorder to identify one or more filter weights of W_(PA) and W_(F) toupdate. In optimal adaptation schemes, PA filter adaptation circuit 124and FIR adaptation circuit 126 may determine an update for each weightof W_(PA) and W_(F), such as an optimal update for each weight tominimize the square error of an error signal (in the case of LMS) or tominimize a cost function (in the case of RLS). Accordingly, in certainaspects of this disclosure, the adaptation engine of cancelationcircuitry 112 may update the filter weights of W_(PA) and W_(F) with anadaptation scheme, such as e.g. LMS or RLS, which may include switchingcircuit 128 alternating between update of W_(PA) and W_(F) by activatingone of either PA filter adaptation circuit 124 or FIR filter adaptationcircuit 126 at a time. Accordingly, one of either W_(PA) and W_(F) willbe updated during each update iteration at time t and the weightadjustments will be reflected in application of W_(PA) and W_(F) toX(t+1) by PA filter circuit 118 and FIR filter circuit 120.

While application of such optimal update schemes (i.e. to update eachfilter weight) to the decoupled filters W_(PA) and W_(F) is within thescope of the solution presented in this disclosure, such schemes may beoverly complex due to the need to calculate an update for each filterweight. Accordingly, the adaptation engine may instead select a reducednumber of filter weights (i.e. only some of the filter weights) toupdate at a time. For example, in update iterations where PA filteradaptation circuit 124 is activated by switching circuit 128 (and thusFIR filter adaptation circuit 126 is deactivated), PA filter adaptationcircuit 124 may compare z(t) and X(t) and identify a single weight ofW_(PA) that makes the greatest contribution to the self-interferenceresidue remaining in z(t), i.e. that is ‘most accountable’ forun-canceled self-interference in z(t). PA filter adaptation circuit 124may then only calculate an update for the identified weight of W_(PA)during the current update iteration. If switching circuit 128 selects toupdate W_(PA) again during the next update iteration, PA filteradaptation circuit 124 may compare z(t+1) and X(t+1) (i.e. the cleansignal and kernel matrix for the next time t+1) and again select asingle weight of W_(PA) to update. As the update occurs at the next timet+1, the clean signal z(t+1) may reflect the change in W_(PA) as e(t+1)will directly depend on the updated weight. FIR filter adaptationcircuit 126 may similarly select single weights of W_(F) to updateduring each update iteration for which FIR filter adaptation circuit 126is activated by switching circuit 128.

Accordingly, instead of updating all or some of the filter weights ofW_(PA) and W_(F) during each update iteration, the adaptation engine mayselect only one weight of W_(PA) or W_(F) (depending on the selection byswitching circuit 128) to update during each update iteration. Suchadaptation schemes are commonly known as Coordinate Descent (CD), whereupdates are made in only a single direction at a time. As previouslydetailed regarding LMS and RLS, adaptive algorithms may aim to reduce asquared error term or a cost function; accordingly, LMS-CD may update asingle weight in order to reduce the squared error term while RLS-CD mayupdate a single weight in order to reduce a cost function. While theadaptation engine of cancelation circuitry 112 may employ any of anumber of different adaptation schemes to update W_(F) and W_(PA), anadvantageous solution of this disclosure may utilize an RLS-DCD schemein which a single weight of W_(F) or W_(PA) (depending on the currentselection of switching circuit 128) is updated using a singlebit-inversion in order to minimize a cost function derived from X(t) andz(t). Accordingly, in each update iteration, the appropriate adaptationengine (PA filter adaptation circuit 124 or FIR filter adaptationcircuit 126) may evaluate X(t) and z(t) to identify which filter weight(of W_(PA) or W_(F)) is the worst-offender in terms of uncanceledleakage in z(t) and to identify which bit of a binary representation ofthe selected weight should be inverted, or ‘flipped’, in order to reducethe cost function. Accordingly, this single-bit inversion update of asingle weight may yield the ‘Dichotomous’ Coordinate Descentnomenclature while the minimization of a cost function (namely theuncanceled residue in z(t) represented by the cross-correlation betweenX(t) and z(t)) may yield the RLS designation. It is nevertheless notedthat other adaptation algorithms may be integrated mutatis mutandis inplace of the RLS-DCD algorithm to update the decoupled weights of W_(PA)and W_(F).

FIGS. 3 and 4 further illustrate the update iterations 212 and 214 ofmethod 200, where PA filter adaptation circuit 124 and FIR filteradaptation circuit 126 may respectively update W_(PA) and W_(F)depending on the current selection by switching circuit 128. PA updateiteration 212 may involve largely identical calculations to FIR updateiteration 214, where the only substantial difference involves thecalculation of the decoupled input signals X_(PA)(t) and X_(F)(t). Aswill be later detailed, the adaptation engine may thus be able to re-usethe same shared circuitry for update iterations 212 and 214. Withoutloss of generality, the context depicted in FIGS. 3 and 4 and detailedbelow corresponds to a RLS-DCD adaptation algorithm in which where PAfilter adaptation circuit 124 and FIR filter adaptation circuit 126 aimto minimize the uncanceled leakage residue in z(t) by selecting a singlebit to invert of a selected filter weight of W_(PA) or W_(F). However,other adaptation algorithms, such as based on LMS, CD, gradient descent,etc., may also be employed to update W_(PA) and W_(F) in a decoupledmanner while remaining within the scope of this disclosure.

As shown in FIG. 3 , PA filter adaptation circuit 124 may firstcalculate decoupled PA input signal X_(PA)(t) in 212 a asX_(PA)(t)=X(t)W_(F), where X_(PA)(t) is of dimension 1×K and each k-thelement of X_(PA)(t) is representative of the M taps of the k-th kernelof X(t). Accordingly, PA filter adaptation circuit 124 may ‘fix’ theweights of W_(F) and only pursue update of W_(PA). As previouslyindicated, PA filter adaption circuit 124 may compare X(t) to z(t) inorder to identify which weights of W_(PA) are contributing to uncanceledleakage in z(t). More specifically, PA filter adaptation circuit 124 mayutilize the cross-correlation β_(PA)(t) between X_(PA)(t) and z(t) inorder to identify which elements of X_(PA)(t) are substantiallycorrelated with z(t), thus allowing PA filter adaptation circuit 124 toidentify the weights of W_(PA) corresponding to the correlated elementsof X_(PA)(t) as requiring update. As PA filter adaptation circuit 124may need the correlations R_(PA)(t) between each of the samples ofX_(PA)(t) in order to calculate the proper update, PA filter adaptationcircuit 124 may also calculate correlation matrix R_(PA)(t).

Accordingly, in 212 b PA filter adaptation circuit 124 may calculatecross-correlation vector β_(PA)(t) (of dimension 1×M) in 212 b as

β_(PA)(t)=λ(β_(PA)(t−1)−sign(β_(PA,max))αR _(PA)(t−1)^((n)))+X _(PA)^(H)(t)z(t)  (7)

and correlation matrix R_(PA)(t) as

R _(PA)(t)=λR _(PA)(t−1)+X _(PA) ^(H)(t)X _(PA)(t)(diag.)  (8)

where λ is a forgetting factor, sign(β_(PA,max))αR_(PA)(t−1)^((n)) an isupdate vector that updates β_(PA)(t) according to the filter weightupdate of the n-th element of W_(PA) from the previous iteration at t−1,and (diag.) indicates that only the diagonal elements of R_(PA)(t) areupdated. As will be later detailed, R_(PA)(t−1)(n) may be the n-thcolumn vector of R_(PA)(t−1), where n corresponds to the index of W_(PA)that was updated at the iteration for time t−1. As will also be laterdetailed, the diagonal and non-diagonal elements of R_(PA)(t) may beperformed separately in order to support for an effective hardwarepipeline schedule, e.g. where the diagonal elements of R_(PA)(t) areupdated first in 212 b and are later followed by update of thenon-diagonal elements of R_(PA)(t) in 212 e (e.g. where the diagonalelements of R_(PA)(t) are part of the critical path and thus should beprocessed before the non-diagonal elements to optimize performance).However, in certain aspects of this disclosure all elements of R_(PA)(t)may alternatively be updated in a single procedure. As the update vectorsign(β_(PA,max))αR_(PA)(t−1)^((n)) depends on the previous updateiteration, PA filter adaptation circuit 124 may calculate β_(PA)(t) inthe first update iteration as λβ_(PA)(t−1)+X_(PA) ^(H)(t)z(t), whereβ_(PA)(t−1) is the initialization value of β_(PA) (which may be set toe.g. a zero matrix). R_(PA)(t−1) may likewise be the initializationvalue of R_(PA).

Accordingly, β_(PA)(t) may indicate the cross-correlation betweendecoupled PA input signal X_(PA)(t) and clean signal z(t), which thusindicates the residual uncanceled leakage attributed to each weight ofW_(PA). Accordingly, inaccurate weights of W_(PA) (i.e. weights that donot accurately characterize the corresponding kernel) will producecorresponding elements of β_(PA)(t) that have high magnitude. As thegoal of PA filter adaptation circuit 124 is to minimize β_(PA)(t) (i.e.β_(PA)(t) is the RLS cost function), PA filter adaptation circuit 124may thus aim to update the weights of W_(PA) in order to reduceβ_(PA)(t), thus reducing the uncanceled leakage residue in z(t).

As previously indicated, in an RLS-DCD context PA filter adaptationcircuit 124 may select a single weight of W_(PA) based on β_(PA)(t) andinvert a single bit of W_(PA) in order to minimize β_(PA)(t). This maybe computationally simpler than e.g. updating each weight of W_(PA)and/or calculating an optimum update for each updated weight of W_(PA).As the weights of W_(PA) that make the greatest contribution touncanceled residue will correspond to the elements of β_(PA)(t) with thehighest magnitude, PA filter adaptation circuit 124 may in 212 cidentify the element β_(PA,max) of β_(PA)(t) having the highestmagnitude and the corresponding index n (nϵ{1, . . . , K}) of β_(PA,max)within β_(PA)(t), which PA filter adaptation circuit 124 may then applyto update the n-th weight of W_(PA). As the elements of β_(PA)(t) may becomplex, in an optimal scenario PA filter adaptation circuit 124 may in212 c calculate the Euclidean norm of each element of β_(PA)(t) andidentify the element with the highest magnitude, i.e. max(|β_(PA)(t)|).However, as such may involve the computation of a squares and squareroots (|a+jb|=√{square root over (a²⁺ b²)}), PA filter adaptationcircuit 124 may simplify the computation in 212 c by identifying theelement of β_(PA)(t) with the highest real or imaginary part asβ_(PA,max) (located at index n in β_(PA)(t)), i.e.

β_(PA,max)=max{|Im{β_(PA)(t)}|,|Re{β_(PA)(t)}|}  (9)

Accordingly, while Equation (9) is an approximation such may still allowPA filter adaptation circuit 124 to identify an element of β_(PA)(t)with the highest real or imaginary part, which may likely be one of thehighest if not the highest-magnitude elements of β_(PA)(t). PA filteradaptation circuit 124 may thus identify β_(PA,max) and thecorresponding index n of β_(PA,max) in β_(PA)(t), which may correspondto the n-th weight of W_(PA) thus resulting in PA filter adaptationcircuit 124 identifying the weight of W_(PA) that is selected forupdate.

PA filter adaptation circuit 124 may then update the n-th weight ofW_(PA), W_(PA,n), based on β_(PA,max) and correlation matrix R_(PA)(t).In a conventional RLS-CD update solution (i.e. non-Dichotomous), PAfilter adaptation circuit 124 may update W_(PA,n) in 212 d asW_(PA,n)=W_(PA,n)∓β_(PA,max)/R_(PA)(n,n), i.e. by performing a divisionof β_(PA,max) by the correlation value R_(PA(n,n)) of the n-th elementof X_(PA)(t) with itself (located at the n-th diagonal term of R_(PA)),which may provide the optimal minimization of β_(PA)(t) as achieved byupdate of a single weight. Without loss of generality, PA filteradaptation circuit 124 may alternatively avoid the computationalcomplexity of the divisional operation by instead selecting a single bitof w (i.e. to flip from a 0 to 1 or vice versa). As R_(PA(n,n)) islocated on the diagonal of R_(PA)(t), PA filter adaptation circuit 124may thus need to ensure that the diagonal entries of R_(PA)(t) are up-todate at 214 d. As the non-diagonally entries of R_(PA)(t) will then beused in 214 e to update R_(F)(t), PA filter adaptation circuit 124 mayseparate the update of R_(PA)(t) into diagonal and non-diagonal portionsin order to enable a pipelined clock schedule that shares computationalelements.

As expressed in the algorithmic logic of 212 d in FIG. 3 , PA filteradaptation circuit 124 may check each of the M_(b) bits of w_(PA,n) inorder to identify which of the bits would optimally minimize β_(PA)(t)if inverted. Accordingly, for e.g. M_(b)=8, this may amount to asubtraction of 1, 2, 4, 8, . . . , or 128 from w_(PA,n) (i.e. 2⁰, 2¹, .. . , 2⁷). As the optimal update to w_(PA,n) is −β_(PA,max)/R_(PA(n,n)),PA filter adaptation circuit 124 may aim to determine in 212 d which ofthe possible subtraction values from 2^(M) ^(b) ⁻¹ to 2⁰ thatβ_(PA,max)/R_(PA(n,n)) is closest to. Accordingly, starting with e.g.α=2^(M) ^(b) (although the initiating value of α may be a designparameter and other values other than the most significant bit could bechosen, such as e.g. the second-most significant bit, third-mostsignificant bit, etc.), PA filter adaptation circuit 124 may iteratefrom l=1 to l=M_(b) (e.g. M_(b)=8) in order to determine which α/2satisfies the condition

${❘\beta_{{PA},\max}❘} > {\frac{\alpha}{2}R_{P{A({n,n})}}}$

and, upon identifying the appropriate α/2, take α as the update valuefor W_(PA,n). By identifying the first α for which

${{❘\beta_{{PA},\max}❘} > {\frac{\alpha}{2}R_{P{A({n,n})}}}},{{{or}\frac{❘\beta_{{PA},\max}❘}{R_{P{A({n,n})}}}} > \frac{\alpha}{2}},$

PA filter adaptation circuit 124 may identify the a closest in value toβ_(PA,max)/R_(PA(n,n)), i.e. the optimum update of W_(PA,n) to minimizeβ_(PA)(t). In other words, starting from a possible set of update values2^(M) ^(b) ⁻¹ to 2⁰, PA filter adaptation circuit 124 may identify whichupdate value is closest to the optimum update valueβ_(PA,max)/R_(PA(n,n)) and select the identified update value as α.Flipping the l-th bit (where l gives the iteration for which

${❘\beta_{{PA},\max}❘} > {\frac{\alpha}{2}R_{P{A({n,n})}}}$

is satisfied) may thus produce an update of α (positive or negativedepending on the sign of β_(PA,max)).

Upon identifying update factor α, PA filter adaptation circuit 124 mayflip the l-th LSB bit of w_(PA,n) to update W_(PA,n) as

W _(PA,n) =w _(PA,n)+sign(β_(F,max))α  (10)

where sign(β_(F,max)) preserves the sign of β_(F,max) to ensure thatw_(PA,n) is updated in the proper direction.

Accordingly, upon completion of the update of W_(PA,n) in 212 d, PAfilter adaptation circuit 124 may have selected the ‘worst offender’W_(PA,n) of W_(PA), i.e. the weight of W_(PA) with the highestcontribution (based on having the maximum real or imaginary part) to theuncanceled residue in z(t) and invert a single bit of the selectedweight WPAn in order to minimize β_(PA)(t), which in connection alsominimizes the leakage residue in z(t). PA filter adaptation circuit 124may then complete the update iteration for time t by updating thenon-diagonal elements of R_(PA)(t) in 212 e as

R _(PA)(t)=λR _(PA)(t−1)+X _(PA) ^(H)(t)X _(PA)(t)(non-diag)  (11)

As previously indicated, as the update of β_(PA)(t) in 212 b requiresthe off-diagonal elements of R_(PA)(t−1) for the n-th columnR_(PA)(t−1)^((n)), PA filter adaptation circuit 124 may perform theoff-diagonal update in 212 e separately in order to re-use computationalhardware for both 212 b and 212 e.

Assuming switching circuit 128 proceeds to t+1 with PA filter adaptationcircuit 124 still selected, PA filter adaptation circuit 124 may repeat212 for t=t+1. Switching circuit 128 may be configured to maintain theupdate selection of PA filter adaptation circuit 124 or FIR filteradaptation circuit 126 for multiple iterations before switching, whichmay include maintaining the selection of either PA filter adaptationcircuit 124 or FIR filter adaptation circuit 126 until the selectedfilter W_(PA) or W_(F) converges or switching between PA filteradaptation circuit 124 or FIR filter adaptation circuit 126 according toa predetermined cyclic number of update iterations (e.g. every otheriteration, every 3 iterations, every 10 iterations, etc.). Accordingly,PA filter adaptation circuit 124 may continue to update W_(PA) duringeach iteration by calculating a new X_(PA)(t) based on the new X(t)matrix in 212 a, updating β_(PA)(t) and R_(PA)(t) in 212 b, identifyingthe maximum element β_(PA,max) of β_(PA)(t) and corresponding index n in212 c, selecting a bit to flip of W_(PA,n) by determining a in 212 d,and completing update of R_(PA)(t) in 212 e.

Conversely, when switching circuit 128 selects FIR filter adaptationcircuit 126 for update, FIR filter adaptation circuit 126 may executethe FIR update iteration 214 as shown in FIG. 4 . FIR filter adaptationcircuit 126 may thus calculate decoupled FIR input signal X_(F)(t) in214 a as X_(F)(t)=W_(PA) ^(T)X(t), where X_(F)(t) is of dimension 1×Mand each m-th element represents the joint contribution of all K kernelsto the m-th taps X(t). Likewise to PA update iteration 212, FIR filteradaptation circuit 126 may be configured to evaluate thecross-correlation β_(F)(t) between X_(F)(t) and z(t) in order toidentify which taps of X_(F)(t) are most correlated with z(t), thusidentifying which taps of W_(F) are the ‘worst-offenders’ in terms ofuncanceled residual leakage in z(t). As these taps are accordingly theleast accurate, in accordance with RLS-DCD FIR filter adaptation circuit126 may proceed to select the least accurate tap W_(F,n) and flip asingle bit of W_(F,n) to reduce β_(F)(t), thus reducing the uncanceledleakage in z(t).

Accordingly, in 214 b FIR filter adaptation circuit 126 may calculatecross-correlation vector β_(F)(t) (of dimension 1×M) as

β_(F)(t)=λ(β_(F)(t−1)−sign(β_(F,max))αR _(F)(t−1)^((n)))+X _(F)^(H)(t)z(t)  (12)

and correlation matrix R_(F)(t) as

R _(F)(t)=λR _(F)(t−1)+X _(F) ^(H)(t)X _(F)(t)(diag.)  (13)

where, likewise to PA update iteration 212, λ is a forgetting factor,sign(β_(F,max))αR_(F)(t−1)^((n)) is an update vector that updatesβ_(F)(t) according to the filter weight update of the n-th elementW_(F,n) of W_(F) from the previous iteration at t−1 (with the n-thcolumn of R_(F)(t)), and (diag.) indicates that only the diagonalelements of R_(F)(t) are updated. Likewise to above, FIR filteradaptation circuit 126 may update the diagonal and non-diagonal elementsof R_(F)(t) separately in order to support a hardware pipeline clockschedule that re-uses computational hardware for 214 b and 214 e;however, in various aspects of this disclosure FIR filter adaptationcircuit 126 may alternatively update all elements of R_(F)(t) in asingle procedure. As the update vector sign(β_(F,max))αR_(F)(t−1)^((n))depends on the previous update iteration, FIR filter adaptation circuit124 may calculate β_(F)(t) in the first update iteration asλβ_(F)(t−1)+X_(F) ^(H)(t)z(t), where β_(F)(t−1) is the initializationvalue of β_(F) (which may be set to e.g. a zero matrix). R_(F)(t−1) maylikewise be the initialization value of R_(F).

As in PA update iteration 212, β_(F)(t) may represent thecross-correlation between each tap of decoupled FIR input signalX_(F)(t) and clean signal z(t). Accordingly, FIR filter adaptationcircuit 126 may aim to identify the element of β_(F)(t) with the highestmagnitude, which may point to the element of W_(F) that is leastaccurate. FIR filter adaptation circuit 126 may thus identify index n ofthe maximum-valued element of β_(F)(t) in 214 c as

β_(F,max)=max{|Im{β_(F)(t)}|,|Re{β_(F)(t)}|}   (14)

As detailed above regarding 212 c, identifying the element β_(F,max) ofβ_(F)(t) with the highest real or imaginary part may be lesscomputationally complex than calculating the magnitude (e.g. L2 norm) ofeach element of β_(F)(t). The approximation of Equation (14) maynevertheless generally identify β_(F,max) as an element of β_(F)(t) thathas one of the highest magnitudes.

FIR filter adaptation circuit 126 may thus identify β_(F,max) and theindex n of β_(F,max) within β_(F)(t), where index n also corresponds tothe index of the weight w_(F,n) of W_(F)(t) that is the ‘worst offender’and thus needs to be updated. Likewise as to 212 d, FIR filteradaptation circuit 126 may in 214 d select a single bit of W_(F,n) toflip in order to minimize β_(F)(t). As the optimum update value OfW_(F,n) is given as β_(F,max)/R_(F(n,n)), FIR filter adaptation circuit126 may identify the scale factor αϵ(2₀, 2¹, . . . , 2^(M) ^(b) ⁻¹)(each corresponding to flipping the l-th bit of W_(F,n) for l=1, 2, . .. , M_(b)) to adjust W_(F,n) by.

Accordingly, as shown in FIG. 4 , in 214 d FIR filter adaptation circuit126 may check the condition

${❘\beta_{F,\max}❘} > {\frac{\alpha}{2}R_{F({n,n})}}$

for α=2^(M) ^(b) ⁻¹ to 2⁰ and, if the condition is satisfied, take thecurrent value of α as being closest to the optimum update valueβ_(F,max)/R_(F(n,n)) and update w_(F,n) as

W _(F,n) =W _(F,n)+sign(β_(F,max))α  (15)

thus updating W_(F) to minimize the uncanceled leakage residue indicatedby β_(F)(t).

FIR filter adaptation circuit 126 may then update the off-diagonalelements of R_(F)(t) as

R _(F)(t)=λR _(F)(t−1)+X _(F) ^(H)(t)X _(F)(t)(non-diag.)  (16)

As in the case of PA filter adaptation circuit 124 noted above, FIRfilter adaptation circuit 126 may then proceed to update W_(F)(t) in thenext iteration for t=t+1 with X(t+1) and z(t+1) if switching circuit 128maintains the selection of FIR filter adaptation circuit 126.

As update of PA filter W_(PA) and FIR filter W_(F) are decoupled, eachof PA filter adaptation circuit 124 and FIR filter adaptation circuit126 may be able to compute updates to W_(PA) and W_(F) in an isolatedenvironment, i.e. without having to account for the other dimension. Thecomputational requirements required for each update may be substantiallyreduced in comparison with the two-dimensional case of the K×M filtermatrix W noted above regarding the existing solution. In particular, thecomputational complexity of the correlation matrices R_(PA) and R_(F)may be markedly diminished. More specifically, in the existing solutionthe adaptation engine may be required to compute a KM×KM correlationmatrix R that represents the correlations between each M taps of each Kkernels. In contrast, the adaptation engine of cancelation circuitry 112may only need to calculate K×K PA correlation matrix R_(PA) and M×M FIRcorrelation matrix R_(F). Furthermore, instead of applying the K×Mfilter W to X(t) as in the existing solution, the signal path ofcancelation circuitry 112 may only apply a K×1 PA filter vector W_(PA)and M×1 FIR filter vector W_(F).

Various advantageous modifications have been noted above regardingcancelation circuitry 112, including the use of RLS-DCD (as opposed togradient descent, traditional coordinate descent, etc.) and identifyingthe maximum magnitude on account of the highest real or imaginarycomponent. These simplifications are optional, and may or may not beutilized along with the decoupled filter application and adaptationwhile still remaining within the scope of this disclosure. Theadaptation engine may optionally also employ a variety of furthertechniques in order to reduce the required computational complexity,including reduced matrix storage, preprocessing calculation stages, andspecific pipelining schedules that allow for re-use of hardware duringdifferent clock cycles.

FIG. 5 shows a matrix memory storage scheme that the adaptation engineof cancelation circuitry 112 may employ in order to both reduce theamount of required memory and required calculations during each PA andFIR update iteration in 212 and 214, respectively. As previouslyindicated, matrix memory 116 may store the M most recent samples foreach of the K kernels, which as shown in FIG. 1 may also be provided toPA filter adaptation circuit 124 and FIR filter adaptation circuit 126for calculation of X_(PA)(t), X_(F)(t), R_(PA)(t), R_(F)(t), β_(PA)(t),and β_(F)(t).

FIG. 6 shows a more detailed architecture of cancelation circuitry 112,which may correspond to the matrix storage scheme of FIG. 5 . As shownin FIG. 6 , kernel generation circuit 114 may provide the kernel outputsX_(t) ^((1:K)) for time t to the signal path and adaptation engine ofcancelation circuitry 112. In the implementation of FIG. 6 , matrixmemory 116 may be located in the adaptation engine and accordingly maystore the KM samples X_(t:t−M+)1^((1:K)) for use in updating W_(PA) andW_(F). This K×M storage is thus reflected in the matrix storage schemeof FIG. 5 . Likewise, FIR filter memory 624 and PA filter memory 626 mayeach store the respective M and K weights of W_(F) and W_(PA), which maysimilarly be stored at filter memory 610 of the signal path.

In a general description of the operation of cancelation circuitry 112as shown in FIG. 6 , processing element 606 may apply W_(PA) and W_(F)to X(t) as previously detailed. In order to reduce hardware complexityand area, processing element 606 may utilize a pipelined approach inorder to apply W_(PA) and W_(F) to X(t). In the example of FIG. 6 ,processing element 606 may be composed of e.g. 8 complex multipliers and7 complex adders and may apply W_(PA) and W_(F) to X(t) over four cycles(although it is noted that numerous other implementations including afull, single-cycle (i.e. non-pipelined) implementation are within thescope of this disclosure). As noted above, processing element 606 maycalculate e(t) as W_(PA) ^(T)X(t)W_(F), which processing element 606 mayperform over e.g. four clock cycles for M=24 and K=8 as

-   -   a. Clock cycle 1: Compute X_(F,t)(t)=Σ_(i=1) ⁸X_(t)        ^((i))(t)w_(PA,i)    -   b. Clock cycle 2: Compute EEC_(acc(m=1:8))=Σ_(i=1)        ⁸X_(F,t−i+1)(t) W_(F,i)    -   c. Clock cycle 3: Compute EEC_(acc(m=1:16))=Σ_(i=9)        ¹⁶X_(F,t−i+1)(t)w_(F,i)+EEC_(acc(m=1:8))    -   d. Clock cycle 4: Compute EEC_(acc(m=1:24))=Σ_(i=17)        ²⁴X_(F,t−i+1)(t)W_(F,i)+EEC_(acc(m=1:16))        where e(t)=EEC_(acc(m=1:24)), X_(F,t)(t) is the sample of        X_(F)(t) for time t, and EEC_(acc (m=1:24)) denotes the        accumulated estimated echo.

Accordingly, processing element 606 may calculate the most recent sampleX_(F,t)(t) of X_(F)(t) in clock cycle 1 by applying W_(PA) to the Ksamples of X(t) for time t, i.e. the kernel samples for each of the Kkernels. As denoted in clock cycle 1 above, processing element 606 mayapply 8 complex multipliers to calculate X_(t) ^((i))(t)w_(PA,i) fori=1, . . . , 8 and provide each intermediate product to accumulationcircuit 614, which may sum each intermediate product to obtain X F.Accumulation circuit 614 may then provide each X Ft (0 to register 602,which may hold the M samples of X_(F)(t), e.g. as a first-in-first-outbuffer where the oldest sample from time t−M is pushed out and thenewest sample for time t is entered. Accordingly, the signal path ofprocessing circuit 112 may avoid performing the entire multiplication ofX_(F)(t)=W_(PA) ^(T)X(t) and instead calculate a single sampleX_(F,t)(t) at each time t and store the results in register 602.

Processing element 606 may then calculate e(t) in clock cycles 2-4 byapplying W_(F)(t) to X_(F)(t). As detailed above for clock cycles 2-4,processing element 606 may employ the 8 complex multipliers to calculate8 samples X_(F,t−i+1)w_(F,i) for i=1:8, i=9:16, and i=17:24. Processingelement 606 may provide each of the intermediate productsX_(F,t−i+)1w_(F,i) to accumulation circuit 616, which may sum each ofthe 8 intermediate products for each clock cycle to obtain e(t) as theaccumulated estimated echo EEC_(acc(m=1:24)). Accumulation circuit 616may then provide e(t) to cancelation circuit 122, which may thensubtract e(t) from received signal y(t) to obtain clean signal z(t).Depending on the accuracy of W_(PA) and W_(F), clean signal z(t) may belargely free of self-interference.

As shown in FIG. 6 , multiplexers 604 and 612 may provide theappropriate selection of 8 samples from X_(F)(t), X(t), W_(F), andW_(PA) to processing element 606 in accordance with the equationsprovided above for clock cycles 1-4. The multiplexer selection signalsmay be provided by FSM 608, which may utilize a finite state machinelogic to cycle through the appropriate multiplexer selection signals.

As previously detailed above regarding FIGS. 1-4 , the adaptation engineof cancelation circuitry 112 may be responsible for adaptively updatingW_(PA) and W_(F) based on X(t) and z(t) in order to enhance theestimation accuracy of e(t) and thus improve the self-interferencecancelation offered by cancelation circuitry 112. As shown in FIG. 6 ,matrix memory 116 may receive the kernel samples X_(t) ^((1:K)) at eachtime t from kernel generation circuit 114 and may subsequently storeeach of the kernel outputs from the M previous samples, i.e. X_(t:t−M+1)^((1:K)), as X(t). As illustrated in the matrix storage scheme of FIG. 5, matrix memory 114 may store the entire K×M entries of X(t).

Matrix memory 116 may provide the current X(t) to PA update circuit 622and FIR update circuit 628, which may be respectively responsible forcalculating X_(PA)(t) and X_(F)(t) in 212 a and 214 a based on X(t) andW_(F) and W_(PA) provided by FIR filter memory 624 and PA filter memory626. As shown in FIG. 6 , PA update circuit 622 and FIR update circuit628 may provide X_(PA)(t) and X_(F)(t) to PA kernel adaptation circuit620 and FIR delay taps adaptation circuit 630, which may eachrespectively store the K and M samples of X_(PA)(t) and X_(F)(t).

PA kernel adaptation circuit 620 and FIR delay taps adaptation circuit630 may then calculate R_(PA)(t), β_(PA)(t), R_(F)(t), add β_(F)(t) in212 b and 214 b. However, as shown in the matrix storage scheme of FIG.5 , PA kernel adaptation circuit 620 and FIR delay taps adaptationcircuit 630 may avoid calculating and storing the entire K×K and M×Mmatrices for R_(F)(t) and R_(PA)(t) and may instead store only the upperrow of R_(F)(t) and the upper triangle of R_(PA)(t), thus conservingconsiderable storage and reducing the computational demands.

More specifically, as R_(PA)(t) is the correlation between each of thekernels of X_(PA)(t) with one another, R_(PA)(t) will be a Hermitianmatrix, where the lower triangle of off-diagonal elements is equal tothe complex conjugate of the upper triangle of off-diagonal elements.Accordingly, instead of calculating the entire M×M matrix for R_(PA)(t),PA kernel adaptation circuit 620 may instead in 212 b calculate theupper triangle of R_(PA)(t) (including the diagonal elements) andconsequently only store the upper triangle elements of R_(PA)(t). Forany subsequent calculations involving lower triangle elements ofR_(PA)(t), PA kernel adaptation circuit 620 may take the complexconjugate of the corresponding upper-triangle element in order to obtainthe lower triangle element.

Regarding R_(F), as noted above R_(F)(t) may be the correlation betweeneach of the taps of X_(F)(t) with one another. While R_(F)(t) may alsobe Hermitian, each row of R_(F)(t) may share considerable statisticalsimilarities given the relationship between each tap and the fact thatthe kernel dimension is fixed during update of W_(F). In other words,the first row of R_(F)(t), which gives the correlations between thefirst tap of X_(F)(t) and each of the remaining M−1 taps of X_(F)(t),may be increasingly similar to the other rows of R_(F)(t), which maylikewise give the correlations between a given tap of X_(F)(t) and theother taps of X_(F)(t). As each of the taps are proximate in time, itfollows that each row may be approximately similar to the other rows;accordingly, without loss of generality, as opposed to calculating theentire M×M matrix or even the upper triangle of R_(F)(t) FIR delay tapsadaptation circuit 630 may instead calculate and store only a single rowof R_(F)(t), e.g. the first row of R_(F)(t). FIR delay taps adaptationcircuit 630 may then utilize the single row of R_(F)(t) as anapproximation when using R_(F(n,m)) and R_(F) (t−1)^((n)). While thismay act as an approximation, FIR delay taps adaptation circuit 630 mayreduce storage and computational requirements through only storing asingle row of R_(F)(t).

Accordingly, in 212 d and 214 d when R_(PA)(t) and R_(F)(t) are neededin determining update factor α, PA kernel adaptation circuit 620 maysimply retrieve R_(PA(n,n)) (which is a diagonal element and thus willbe explicitly stored as part of the upper triangle) while FIR delay tapsadaptation circuit 630 may retrieve R_(F(1,1)) regardless of n. As theactual value of R_(F(n,n)) gives the correlation between the n-th tapand itself, R_(F(1,1)) may serve as a suitable approximation as thecorrelation of the n=1 tap with itself. As can be seen from the matrixstorage scheme illustrated in FIG. 5 , this implementation may lead toconsiderable reductions in both storage and computational demands on theadaptation engine.

As shown in FIG. 6 , PA kernel adaptation circuit 620 and FIR delay tapsadaptation circuit 630 may each provide index n and weight WPA,n/w_(F,n)to controller/FSM 618, which may proceed to instruct filter memory 610to update the corresponding n-th element of W_(PA)/W_(F) with thespecified weight w_(PA,n)/w_(F,n). As such may involve a DCD updatescheme of only a single bit, controller/FSM 618 may simply identify theweight index n and bit index m that needs to be flipped, thus promptingfilter memory 610 to flip the m-th bit of the n-th weight ofW_(PA)/W_(F). Controller/FSM 618 may additionally include switchingcircuit 128 and thus may be responsible for selecting which of PA filteradaptation circuit 124 or FIR filter adaptation circuit 126 to activate.

In addition to the matrix storage scheme, the adaptation engine ofcancelation circuitry 112 may additionally reduce the computationalrequirements involved in calculating X_(PA)(t) and X_(F)(t) at PA updatecircuit 622 and FIR update circuit 628. FIG. 7A shows an illustration ofthe matrix multiplication X_(PA)(t)=X(t)W_(F), where each k-th elementof X_(PA)(t) for k=1, . . . , K may be the dot product of W_(F) with thek-th row X(t). As denoted in FIG. 7A, the k-th element X_(PA,k)(t) ofX_(PA)(t) may then be given as

X _(PA,k)(t)=X _(t) ^((k)) w _(F,1) +X _(t−1) ^((k)) w _(F,2) + . . . +X_(t−M+1) ^((k)) w _(F,M)  (17)

where w_(F,m) gives the m-th tap of W_(F).

Accordingly, only the first sum term X_(t) ^((k))w_(F,1) will depend onthe current input sample at time t while all of the remaining sum termsX_(t) ^((k))w_(F,2),X_(t−2) ^((k))w_(F,3), . . . , X_(t−M+1)^((k))w_(F,M) depend on past samples from times t−1 and previous.Accordingly, as opposed to requiring the calculation of KM total sumterms required to calculate all of the K elements of X_(PA)(t) afterreceiving the most recent X_(t) ^((1:K)), PA update circuit 622 maypre-calculate and sum the) past sum terms X_(t−1) ^((k))w_(F,2),X_(t−2)^((k))w_(F,3), . . . , X_(t−M+1) ^((k) w) _(F,M) for k=1, . . . , K atan earlier time and, after calculating w_(F,1)X_(t) ^((1:K)), simply addthe preprocessing sum terms to w_(F,1)X_(t) ^((1:K)) to obtain the fullX_(PA)(t). PA update circuit 622 may therefore only need to havesufficient hardware to calculate K sum terms for X_(t) ^((1:K))w_(F,1),and thus may re-use this hardware to calculate the other sum terms at anearlier time (which may additionally require memory for K extra terms asshown for X_(PA_pre)(t) in FIG. 5 ). While the required computations maybe the same, this may substantially reduce the hardware arearequirements of PA update circuit 622, thus directly reducingmanufacturing costs.

FIR update circuit 628 may also drastically simplify the calculation ofX_(F)(t) in 214 a. As shown in FIG. 7B, since W_(PA) is fixed duringupdate of W_(F), each of the M elements of X_(F)(t) may be time-delayedweighted inputs of one another. Accordingly, FIR update circuit 628 maynot need to calculate all M samples of X_(F)(t) for each time t;instead, FIR update circuit 628 may utilize a first-in-first-out bufferapproach (similar to as detailed above regarding buffer 602) andcalculate X_(F,t)(t), i.e. the sample of X_(F)(t) for time t, to bestored with the previous M−1 samples of X_(F)(t). The oldest sample ofX_(F)(t), i.e. from time t−M, may then be discarded every time a newsample X_(F,t)(t) is calculated. As such may reduce the requiredcomputations from MK multiplications and M(K−1) additions to Kmultiplications and K−1 additions, FIR update circuit 628 may saveconsiderably reduce complexity and the required hardware area.

Accordingly, PA update circuit 622 may employ pre-processing in order toreduce the hardware requirements for calculating X_(PA)(t) while FIRupdate circuit 628 may utilize the time-delayed weighted relationship toreduce the computational requirements for calculating X_(F)(t). As notedabove, these modifications are optional and may or may not beimplemented in various aspects of this disclosure.

Due to the complexity involved in self-interference estimation, a keyconstraint in many self-interference cancelation designs is hardwarearea. As noted above, the preprocessing modification of PA updatecircuit 622 may reduce the number of multiplication and additionhardware elements needed as PA update circuit 622 may only need toperform K multiplications with the current kernel samples X_(t) ^((1:K))followed by K additions with each of the K preprocessing sum terms toobtain X_(PA)(t). PA update circuit 622 may then perform the K(M−1)complex multiplications and K(M−2) complex additions by re-using thesame hardware during other clock cycles. The adaptation engine ofcancelation circuitry 112 may utilize further hardware computationschedules in order to re-use hardware and thus reduce the hardwarerequirements of cancelation circuitry 112. As noted above, such hardwarescheduling is optional and thus may or may not be utilized in variousaspects of this disclosure.

FIG. 8 depicts an exemplary hardware computation schedule for PAadaptation circuit 124 (PA update circuit 622, PA kernel adaptationcircuit 620, and controller/FSM 618) and FIR adaptation circuit 126 (FIRupdate circuit 628, FIR delay taps adaptation circuit 630, andcontroller/FSM 618). Tables 810 and 830 show the total numbers ofmultipliers and adders (as will be further detailed) that the adaptationengine may utilize for each operation while hardware schedules 820 and840 depict the computational operations executed by PA adaptationcircuit 124 and FIR adaptation circuit 126 during each clock cycle. Asshown in hardware schedules 820 and 840, both PA adaptation circuit 124and FIR adaptation circuit 126 may utilize 5 clock cycles in order tocomplete a single update of W_(PA) and W_(F) for a given sample t.

As shown in PA branch schedule 820, PA update circuit 622 may calculatethe preprocessing sum terms X_(t−1) ^((k))w_(F,2),X_(t−2) ^((k))w_(F,3),. . . , X_(t−M+1) ^((k))w_(F,M) for k=1, . . . , K of X_(PA)(t) as notedabove regarding Equation (17) in ‘hidden’ clock cycles (denoted asshaded cycles in hardware schedule 820), which may be distributed at anytime prior to the start of calculations for sample time t. As denoted inthe exemplary context of FIG. 8 , M and K may be set to M=24 and K=8;accordingly, PA update circuit 622 may reuse the same computationhardware over multiple clock cycles. As shown in hardware schedule 820,PA update circuit 622 may utilize e.g. 2(M−1) complex multipliers and2(M−2) complex adders in order to support calculation of thepreprocessing sum terms X_(t−1) ^((k))w_(F,2),X_(t−2) ^((k))w_(F,3), . .. , X_(t−M+1) ^((k))w_(F,M) for two k indices at a time; e.g. for k=1,2in clock cycle 0, k=3,4 in clock cycle 1, k=5,6 in clock cycle 2, andk=7,8 in clock cycle 3. The amount of computation hardware may beadjusted to various different with varying tradeoffs between the numberof clock cycles and hardware area.

PA update circuit 622 may then apply a subset of the same complexmultipliers and adders to calculate the sum terms for the kernels oftime t, X_(t) ^((1:K)), as w_(F,1)X_(t) ^((1:K)), during clock cycle 0and add the sum terms to the preprocessing sum terms to obtain X_(PA)(t)(212 a). As each element X_(PA)(t) is needed to calculate β_(PA)(t), PAkernel adaptation circuit 620 may begin the update of β_(PA)(t) (212 b)in clock cycle 1. In order to reduce the hardware requirements, PAkernel adaptation circuit 620 may update β_(PA)(t) over both clockcycles 1 and 2, thus only requiring 4 complex multipliers and 4 complexadders as denoted in table 810 while still avoiding any datadependencies. PA kernel adaptation circuit 620 may also beginidentifying β_(PA,max) and n (212 c) in clock cycle 2 with the elementsof β_(PA)(t) calculated in clock cycle 1 and completing theidentification of β_(PA,max) and n in clock cycle 3 with the remainingelements of β_(PA)(t) calculated in clock cycle 2. PA kernel adaptationcircuit 620 may simultaneously begin updating R_(PA)(t) (212 b) in clockcycle 3, which may be completed in clock cycle 4 (212 e). As previouslyindicated, PA kernel adaptation circuit 620 may update the diagonalelements of R_(PA)(t) in the clock cycle 3 and the non-diagonal elementsof R_(PA)(t) in clock cycle 4 in order to avoid data dependency issuesrelated to the use of R_(PA(n,n)) in identifying β_(PA,max).

While completing update of R_(PA)(t) in clock cycle 4, PA kerneladaptation circuit 620 may concurrently perform the DCD update scheme inorder to identify α, i.e. the bit of w_(PA,n) that will be flipped. PAkernel adaptation circuit 620 may provide n and a to controller/FSM 618,which may complete the update of W_(PA) by updating W_(PA,n) accordingto α during the next clock cycle, which PA update circuit 622 mayconcurrently utilize as clock cycle 0 to calculate w_(F,1)X_(t+1)^((1:K)) for the next time t+1.

FIR adaptation circuit 126 may similarly utilize a specific 5-clockcycle as shown in hardware schedule 840. As FIR update circuit 628 mayonly need to perform M multiplications and M−1 additions to calculateX_(F)(t) (due to the time-delayed weighted relationship noted above),FIR adaptation circuit 126 may not need to perform any preprocessingstages in hidden clock cycles. Accordingly, FIR update circuit 628 mayapply M complex multipliers and M−1 complex adders in clock cycle 0 tocalculate X_(F)(t) (214 a). FIR delay taps adaptation circuit 630 maysimilarly use a staggered clock cycle scheme in clock cycles 1-4 inorder to update β_(F)(t), R_(F)(t), and identify n and β_(F,max) (214 band 214 c). FIR delay taps adaptation circuit 630 may then apply the DCDscheme to determine α (214 d) in clock cycle 4 and provide n and a tocontroller/FSM 618 for update of w_(F,n) in the following clock cycle 0of the next update. FIR delay taps adaptation circuit 630 may likewisecalculate the diagonal elements of R_(F)(t) in clock cycle 3 and thenon-diagonal elements of R_(F)(t) in clock cycle 4 in order to avoiddata dependency issues.

The schedules and hardware resource tables depicted in FIG. 8 may thusprovide an efficient implementation that offers an advantageous tradeoffbetween latency and hardware area. Numerous other schedules and hardwarearchitectures are also within the scope of this disclosure.

The individual components of cancelation circuitry 112 detailed abovemay be structurally realized/embodied as hardware logic, e.g. as one ormore integrated circuits or FPGAs, as software logic, e.g. as one ormore processors executing program code that defining arithmetic,control, and I/O instructions stored in a non-transitorycomputer-readable storage medium, or as a combination of hardware andsoftware logic. Accordingly, while the individual components ofcancelation circuitry 112 are depicted separately in FIG. 1 and FIG. 6 ,this depiction merely serves to highlight the operation of cancelationcircuitry 112 on a functional level; consequently, one or more of thecomponents of cancelation circuitry 112 may be integrated into a commonhardware and/or software element.

Without loss of generality, FIGS. 9-11 illustrate exemplary internalconfigurations of PA update circuit 622, FIR update circuit 628, PAkernel adaptation circuit 622, and FIR delay taps adaptation circuit630.

FIG. 9 shows the internal computational and memory elements of PA updatecircuit 622. Corresponding to table 810, PA update circuit 622 mayinclude 2 (M−1) complex mulitpliers and 2(M−2) complex adders for thepreprocessing X_(PA)(t) calculations and K complex multipliers andcomplex adders for the current X_(PA)(t) calculation. PA update circuit622 may additionally include the K element memories for X_(PA_pre)(t)and X_(PA)(t) as shown in FIG. 9 . FIR update circuit 628 shown in FIG.10 may include the M element X_(F)(t) memory and K complex multipliersand K−1 complex adders for X_(F)(t).

FIG. 11 shows correlation update circuit 1110 and cross-correlationupdate circuit 1120. As the correlation and cross-correlations of PAupdate iteration 212 and FIR update iteration 214 may be identical, bothPA kernel adaptation circuit 620 and FIR delay taps adaptation circuit830 may include multiple correlation update circuits 1110 andcross-correlation update circuits 1120 in order to perform thecalculations needed to obtain R_(PA)(t), β_(PA)(t), R_(F)(t), andβ_(F)(t). The number of correlation update circuits 1110 andcross-correlation update circuits 1120 included in both PA kerneladaptation circuit 620 and FIR Depay taps adaptation circuit 630 maydepend on the M, K, and various factors related to clock cycle/pipelineschedules and hardware area. As shown in FIG. 11 , both correlationupdate circuit 1110 and cross-correlation update circuit 1120 mayinclude a local FSM to direct the clock cycle scheduling, e.g. inaccordance with a hardware schedule such as shown in FIG. 8 ), a set ofprocessing elements (PE) composed of either correlation PEs 1130 orcross-correlation PEs 1140, a matrix memory for holding R(t)/β(t), and ascale control circuit. The capacity and contents of the matrix memoriesmay correspond to whether correlation update circuit 1110 andcross-correlation update circuit 1120 is assigned to PA kerneladaptation circuit 620 or FIR delay taps adaptation circuit 830.

The number of PEs included in each of correlation update circuit 1110and cross-correlation update circuit 1120 may be dictated by the numberof matrix elements that need to be calculated in parallel. As eachcorrelation PE 1130 and cross-correlation PE 1140 may be configured toupdate a single element of R(t)/β(t), PA kernel adaptation circuit 620and FIR delay taps adaptation circuit 630 may each include multiplecorrelation update circuits 1110 and multiple cross-correlation updatecircuits 1120 in order to support calculation of multipole updates toR(t)/β(t) in parallel. Such may consequently depend on the desired clockcycle scheduling, such as shown in FIG. 8 . As detailed in table 810, PAkernel adaptation circuit 620 may include e.g. 18 correlation updatecircuits 1110 and e.g. 4 cross-correlation update circuits 1120 for K=8and M=24 in order to enable a 5 clock cycle update iteration. Such mayallow PA kernel adaptation circuit 620 to calculate the 36 totalrequired complex multiplications and additions to update R_(PA)(t)spread over two clock cycles (18 complex multiplications and additionsper clock cycle) and to calculate the 8 total required complexmultiplications and additions to update β_(PA)(t) spread over two clockcycles (4 per complex multiplications and additions per clock cycle).

As noted in table 830, FIR delay taps adaptation circuit 630 may need toinclude e.g. 12 correlation update circuits 1110 and e.g. 12cross-correlation update circuits 1120. Such may thus allow FIR delaytaps adaptation circuit 630 to calculate the 24 total required complexmultiplications and additions to update R_(F)(t) spread over two clockcycles (12 complex multiplications and additions per clock cycle) and tocalculate the 12 total required complex multiplications and additions toupdate β_(FIR)(t) spread over two clock cycles (12 per complexmultiplications and additions per clock cycle).

Due to the equivalence in the calculations for PA and FIR updates andthe decoupled operation mode, PA kernel adaptation circuit 620 and FIRdelay taps adaptation circuit 630 may in certain aspects of thisdisclosure be configured to share the same correlation update circuit1110 and cross-correlation update circuit 1120, i.e. to re-use the samehardware at different times depending on which of PA kernel adaptationcircuit 620 and FIR delay taps adaptation circuit 630 is currentlyupdating W_(PA) or W_(F), respectively. As PA kernel adaptation circuit124 and FIR adaptation circuit 126 operate separately, such may onlyrequire that the shared correlation update circuit 1110 and sharedcross-correlation update circuit 1120 include the proper number ofcorrelation PEs 1130 and cross-correlation PEs 1140 to support both PAand FIR updates, e.g. 18 correlations PEs 1130 and 12 cross-correlationPEs 1140.

As shown in FIG. 11 , each correlation PE 1130 may receive two samplesof X_(PA)(t)/X_(F)(t) to multiply. In order to simplify the input dataswitching overhead, correlation update circuit 1110 may utilize a smartmemory indexing and cycle allocation scheme. FIG. 12 illustrates thesmart memory indexing and cycle allocation scheme for an exemplaryimplementation where correlation update circuit 1110 includes 18correlation PEs 1130 and utilizes two cycles to calculate R_(PA)(t) forK=8 and M=24. As denoted by the shading of table 1200, correlationupdate circuit 1100 may optimize the calculation of each element ofR_(PA)(t) by ensuring that each correlation PE 1130 calculates anelement of R_(PA)(t) in the first cycle that is in the same column orrow as the element of R_(PA)(t) calculated in the second cycle. Aseither the column or row remains the same, one input of each correlationPE 1130 may remain the same for both the first and second cycles (asthis input will be same element of X_(PA)(t)). Such is shown by thenumerical indices of table 1200, which indicate which of the 18 totalcorrelation PEs 1130 will calculate the corresponding element ofR_(PA)(t). Additionally, correlation update circuit 1110 may calculatethe diagonal elements of R_(PA)(t) in the first cycle, thus eliminatingthe data dependency that can occur in the pipeline schedule shown inFIG. 8 . Correlation update circuit 1110 may thus utilize the memoryindex shown in table 1210 to index the memory for R_(PA)(t).

The optional enable signal en at each of correlation PEs 1130 andcross-correlation PEs 1140 may allow for configurable operation, e.g.for cancelation circuitry 112 to be utilized for any K′≤K kernels andM′<M taps. Accordingly, the enable signal en may be utilized to disableall unused correlation PEs 1130 and cross-correlation PEs 1140, e.g.K−K′ or M−M′ unused correlation PEs 1130 and cross-correlation PEs 1140.

While optional, the scale control circuits may be included in order tomaintain the stability between W_(PA) and W_(F). As both dimensions aredecoupled in cancelation circuitry 112, it may be possible for theweights to become biased towards either PA or FIR, i.e. where one ofW_(PA) and W_(F) becomes much stronger than the other. Accordingly, thescale control circuitry may be configured to detect if the weightsbecome biased towards one of W_(PA) and W_(F) and, if so, apply a scalefactor in order to counter the bias.

Each of PA kernel adaptation circuit 620 and FIR delay taps adaptationcircuit 830 may additionally include DCD circuit 1310 as shown in FIG.13 , which may be configured to execute the DCD update process toidentify α (212 d/214 d). As for the other modifications introducedabove, this internal configuration of DCD circuit 1310 is exemplary andother realizations are within the scope of this disclosure. Whilemathematically expressed as a for loop in 212 d and 214 d, DCD circuit1310 may be implemented with a parallel architecture, where DCD circuit1310 may evaluate each value of α=2⁰, 2¹, . . . , 2 ^(M) ^(b) ⁻¹ inparallel with e.g. one comparator per hypothesis to evaluate thecomparison

${❘\beta_{\max}❘} > {\frac{\alpha}{2}R_{({n,n})}}$

of 212 d/214 d. As only one comparator may be needed, this may offer asignificant tradeoff between hardware and throughput, thus considerablyfavoring a parallel architecture. DCD circuit 1310 may also beconfigurable to support up to M_(b) bits as the individual a comparatorsmay be left unused.

PA kernel adaptation circuit 620 and FIR delay taps adaptation circuit830 may additionally include maximum cross-correlation detection circuit1410 shown in FIG. 14 , which may be configured to identify β_(max) forβ_(PA)(t) and β_(F)(t) in 212 c/214 c by identifying the element ofβ_(PA)(t)/β_(F)(t) with the largest real or imaginary part using thecomparator and multiplexer logic shown in FIG. 14 . Maximumcross-correlation detection circuit 1410 may additionally preserve thesign of β_(max) in order to update w_(n) in the proper direction.Generally speaking, PA kernel adaptation circuit 620 and FIR delay tapsadaptation circuit 830 may each thus be composed of correlation updatecircuit 1110, cross-correlation update circuit 1120, DCD circuit 1310,and maximum cross-correlation detection circuit 1410.

Accordingly, any of the various modifications noted above may beimplemented as part of cancelation circuitry 112, which may offer avariety of advantages including reduced computational demands andlatency, reduced hardware area, reduced memory requirements, etc.Cancelation circuitry 112 may thus provide a highly effectiveself-interference cancelation system that may be realizable with currenttechnology. Although M and K may be scaled to any values, M=24 and K=8may present an attractive balance between estimation accuracy andcomplexity. When combined with various of the optional modificationsnoted above, such may provide a system that has as much as an 80%hardware reduction compared to the existing ‘non-decoupled’ solution(i.e. with updates of W of dimension K×M). As noted above, cancelationcircuitry 112 may additionally be implemented as a ‘configurable’ designwhere cancelation circuitry 112 may be realized to support up to M tapsand K kernels but can be dynamically configured to performself-interference cancelation with any M′≤M taps and K′≤K kernels.

The self-interference cancelation scheme detailed thus far may utilize amemoryless model of power amplifier 104 (where the FIR weights W_(F) aredesigned to model the various transmit and receive FIR filters inleakage path 130). However, although power amplifiers may generally bedesigned to be memoryless, power amplifiers may in practical scenariosexhibit unintended memory effects. These memory effects may be caused byimperfections such as charging and discharging junctions, thermalvariations, and other physical phenomena and may cause time-dependencieson the power amplifier output. Accordingly, cancelation circuitry 112may be slightly modified in order to model such PA memory effects byadding L>1 taps for each kernel. FIG. 15 shows an exemplaryconfiguration in which W_(PA) is implemented as K×L (with L>1) matrixwhere each kernel is thus modeled over L taps (as opposed to thememoryless design previously detailed with L=1). Using W_(PA) defined asa long vector

$\begin{matrix}{W_{PA} = \begin{bmatrix}w_{{PA},1,1} \\w_{{PA},1,2} \\\ldots \\w_{{PA},1,L} \\w_{{PA},2,1} \\\ldots \\w_{{PA},2,L} \\\ldots \\w_{{PA},K,1} \\\ldots \\w_{{PA},K,L}\end{bmatrix}} & (18)\end{matrix}$

PA filter circuit 118 may apply W_(PA) to X(t) to obtain X_(F) definedas

X _(F) =[X _(F,t) ,X _(F,t−1) , . . . ,X _(F,t−M+)1]  (19)

where each entry X_(F,j) is calculated as

$\begin{matrix}{X_{F,j} = {W_{PA}^{H}\begin{bmatrix}X_{t}^{(1)} \\X_{t - 1}^{(1)} \\\ldots \\X_{t - L + 1}^{(1)} \\X_{t}^{(2)} \\X_{t - 1}^{(2)} \\\ldots \\X_{t - L + 1}^{(2)} \\\ldots \\x_{t}^{(K)} \\x_{t - 1}^{(K)} \\\ldots \\X_{t - L + 1}^{(K)}\end{bmatrix}}} & (20)\end{matrix}$

PA filter adaptation circuit 124 may thus be configured to adapt each ofthe KL weights of W_(PA) in order to fully approximate the L taps of thePA response.

FIG. 16 shows method 1600 of method of performing interferencecancelation. As shown in FIG. 16 , method 1600 includes separatelyapplying a kernel dimension filter and a delay tap dimension filter toan input signal for an amplifier to obtain an estimated interferencesignal (1610), subtracting the estimated interference signal from areceived signal to obtain a clean signal (1620), and alternating betweenupdating the kernel dimension filter and updating the delay tapdimension filter using the clean signal (1630).

FIG. 17 shows method 1700 of performing interference cancelation. Asshown in FIG. 17 , method 1700 includes obtaining one or more subsignalsderived from an input signal for an amplifier (1710), each of the one ormore subsignals representing a non-linear component of an amplifierresponse and composed of a plurality of delay taps, separately applyinga first filter and a second filter to the one or more subsignals toobtain an estimated interference signal (1720), wherein the first filterapproximates the amplifier response over the one or more subsignals andthe second filter approximates the amplifier response over the pluralityof delay taps (1730), subtracting the estimated interference signal froma received signal to obtain a clean signal, and alternating betweenupdating the first filter and updating the second filter using the cleansignal (1740).

In one or more further exemplary aspects of the disclosure, one or moreof the features described above in reference to FIGS. 1-15 may befurther incorporated into method 1600 and/or 1700. In particular, method1600 and/or 1700 may be configured to perform further and/or alternateprocesses as detailed regarding cancelation circuitry 112 and/orcommunication circuitry 100.

Furthermore, the implementations of cancelation circuitry 112 shown inFIGS. 1 and 4 include only a single signal path, which may beappropriate for a Single Input Single Output (SISO) configuration withone receive chain and one transmit chain. FIGS. 18-20 detail severaldifferent configurations that may be employed in MIMO cases havingmultiple transmit and receive chains. Each receive chain may thereforeneed to include self-interference cancelation circuitry in order toremove leakage from received signals; however, as each of the transmitchains may produce leakage onto each receive chain, theself-interference cancelation circuitry for each receive chain may needto estimate and cancel leakage from each transmit chain. Accordingly,each of the receive chains may need to have a different W_(F) and W_(PA)(assuming use of a bilinear cancelation architecture) for each transmitchain. For example, for an N×N MIMO scheme each of the N receive chainmay need to have N FIR filters W_(F,1:N) and N PA filters W_(PA,1:N),i.e. one per transmit chain, in order to produce estimated interferencesignals e_(1:N)(t) for summation to obtain the combined interferencesignal e(t) (where each receive chain produces a separate e(t) fromseparate e_(1:N)(t)). As each transmit chain utilizes a different poweramplifier and has a different data5 stream, each receive chain mayadditionally generate a separate kernel matrix X_(1:N)(t) for eachtransmit chain to utilize along with the clean signal z(t) to calculateupdates to W_(F,1:N) and W_(PA,1:N). Such may be extended to MIMOschemes of any dimensions with any number of transmit receive chains.

Such MIMO applications may unavoidably increase the signal pathcircuitry and memory requirements for an employed SIC scheme due to theneed to store and apply a separate W_(F,1:N), W_(PA,1:N), and X_(1:N)(t)per each of the N receive chains; accordingly each receive chain mayhave a separate kernel generation circuit 114, matrix memory 116, PAfilter circuit 118, and FIR filter circuit 120 for each of the Ntransmit chains. FIG. 18 illustrates such a configuration forcancelation circuitry 1800 that may be employed in the case of tworeceive chains, such as e.g. for a 2×2 MIMO scheme. As shown in FIG. 18, cancelation circuitry 1800 may therefore include multiple ‘duplicates’of certain components in order to perform the estimation of the leakagesignals from each transmit chain, such as kernel generation circuits 114a and 114 b, matrix memories 116 a and 116 b, PA filter circuits 118 aand 118 b, FIR filter circuits 120 a and 120 b.

As the power amplifiers have separate input transmit signals in s₁(t)and s₂(t) and additionally utilize different antennas, cancelationcircuitry 1800 may utilize a separate kernel generation circuit for eachpower amplifier in kernel generation circuits 114 a and 114 b.Accordingly, kernel generation circuits 114 a and 114 b may each bothreceive the input transmit signals s₁(t) and s₂(t) at each time t forthe power amplifiers of both transmit chains and generate kernel samplesX_(t) ^((1,1:K)) and X_(t) ^((2,1:K)) to provide to matrix memories 116a and 116 b. Matrix memories 116 a and 116 b may each retain the past Mkernel samples for each transmit chain as K×M matrices X₁(t) and X₂(t),which each may provide respectively to PA filter circuits 118 a and 118b for preprocessing. PA filter circuits 118 a and 118 b may then applythe respective PA filters W_(PA,1) and W_(PA,2) as W_(PA,1) ^(T)X₁(t)and W_(PA,2) ^(T)X₂(t), which may each be a K×1 weight vector thatmodels the K kernels of the respective power amplifier (and each maycontain respective PA weights W_(PA,k) ^((b)) for k=1, . . . , K, whereb=1 or 2 depending on which PA filter). PA filter circuits 118 a and 118b may then provide the resulting X_(PA,1)(t) and X_(PA,2)(t) to FIRfilter circuits 120 a and 120 b. FIR filter circuits 120 a and 120 b maythen apply respective FIR filters W_(F,1) and W_(F,2) (and each maycontain respective FIR weights w_(F,m) ^((b)) for m=1, . . . , M) whereb=1 or 2 depending on which FIR filter) as W_(PA,1) ^(T)X₁(t)W_(F,1) andW_(PA,2) ^(T)X₂(t)W_(F,2) to obtain the estimated interference signalse₁(t) and e₂(t) resulting from the first and second transmit chains,respectively. Summation circuit 1802 may then add both estimatedinterference signals to obtain the overall estimated interference signale(t) (for the first receive chain) as e(t)=e₁(t)+e₂(t). Cancelationcircuit 122 may then subtract e (t) from the receive signal y (t) forthe first receive chain to obtain clean signal z(t), which may largelycontain exclusively desired data assuming accurate filter models.

FIG. 18 may also include adaptation circuits 124 a/126 a and 124 b/126 b(respectively composed of PA filter adaptation circuit 124 a/FIR filteradaptation circuit 126 a and PA filter adaptation circuit 124 b/FIRfilter adaptation circuit 126 b), which may each perform the adaptationtechniques detailed above (e.g. a bilinear technique such as RLS-DCD,further detailed regarding FIGS. 2 and 3 for PA update iteration 212 andFIR update iteration 214) for the respective transmit chains tocontinuously update the FIR and PA filters to enable accurateinterference estimation and cancelation. As the adaptations areseparate, adaptation circuits 124 a/126 a and 124 b/126 b may runindependently from one another to update the FIR and PA filters (whereFIR and PA update iterations for each are alternated by fixing onedimension and adapting the other).

In order to reduce the amount of hardware and requisite area forcancelation circuitry 1800, cancelation circuitry 1800 may shareadaptation circuitry instead of employing separate adaptation circuitseach dedicated to a respective transmit chain. Accordingly, instead ofutilizing separate adaptation circuits 124 a/126 a and 124 b/126 b,cancelation circuitry 1800 may instead utilize only one adaptationcircuit, e.g. adaptation circuit 124 a/126 a, that may alternate betweenupdating W_(PA,1) and W_(F,1) for the first transmit chain and W_(PA,2)and W_(F,2) for the second transmit chain and thus handle the adaptationresponsibilities for the filters of both transmit chains. For example,adaptation circuit 124 a/126 a may update W_(PA,1) and W_(F,1) (based onX₁(t) and z(t), which PA adaptation circuit 124 a and FIR adaptationcircuit 126 a may additionally update by alternating in a decoupledswitching fashion) for a predefined cycle of samples or until aconvergence criteria is reached (e.g. for β_(F,1)(t) and/or β_(PA,1)(t)for the first transmit chain) before switching to updating W_(PA,2) andW_(F,2) (based on X₂(t) and z(t), which PA adaptation circuit 124 a andFIR adaptation circuit 126 a may additionally update by alternating in adecoupled switching fashion) for a predefined cycle of samples or untila convergence criteria is reached (e.g. for β_(F,2)(t) and/orβ_(PA,2)(t) for the first transmit chain). As complete convergence mayoccur after several hundred samples, such may enable cancelationcircuitry 1800 to employ a single adaptation engine in adaptationcircuit 124 a/126 a to handle filter adaptation for interferencecancelation of multiple transmit chains, thus considerably reducinghardware.

As each of the N receive chains may require an instance of cancelationcircuitry 1800, this adaptation engine sharing may still require Nadaptation circuits 124 a/126 a, where each adaptation circuit 124 a/126a handles the leakage estimation for N transmit chains for therespective receive chain. Accordingly, in order to further reducehardware requirements, the self-interference cancelation architecturemay expand the adaptation engine sharing between receive chains. FIG. 19shows an example of such in which a single adaptation engine (e.g.adaptation circuit 124 a/126 a, which contains at least one PAadaptation circuit 124 a and one FIR adaptation circuit 126 a) mayhandle the adaptation for multiple instances of cancelation circuitry1800 where each instance of cancelation circuitry 1800 is responsiblefor leakage estimation and cancelation for one receive chain.Accordingly, the adaptation engine may alternate between adaptingW_(PA,n) and W_(F,n), n=1, . . . , N, for each of the N receive chains,e.g. with switching based on a predefined number of samples or aconvergence criteria, and thus may enable a significant reduction inhardware area. While such adaptation resource sharing may necessarilyproduce some performance degradation compared to dedicated adaptationresources, this may be offset by the resulting hardware area reductions.

As shown in FIG. 18 , cancelation circuitry 1800 may employ separate PAand FIR filters to model the leakage from each transmit chain at thereceive chain associated with cancelation circuitry 1800. In the case ofPA filters W_(PA,1) and W_(PA,2), such may be necessary in order toeffectively model the separate power amplifiers in each transmit chain;for example, even if the same power amplifier model or type is used forboth power amplifiers, different filters may be needed to model eachpower amplifier due to the differing input streams in s₁(t) and s₂(t)and differing antennas. However, in the case of FIR filters W_(F,1) andW_(F,2), cancelation circuitry 1800 may be modified to utilize a singleFIR filter W_(F,1) to jointly model the FIR dimension of both transmitchains. More specifically, if the transmit chain FIR filters thatW_(F,1) and W_(F,2) are intended to model are similar (e.g. have asimilar response), cancelation circuitry 1800 may collectively model theFIR filters of both transmit chains with only a single FIR filter W_(F).In other words, if the signal paths for each transmit chain utilizeseparate FIR filters or FIR filters with different weights, the taps ofeach transmit chain may need to be estimated separately from oneanother. However, if each transmit chain uses similar FIR filters, theinterference cancelation circuitry may be simplified considerably as thesimilar FIR filters may be estimated jointly. Such may further reducehardware area requirements and/or reduce the degree of resource sharing.

FIG. 20 shows cancelation circuitry 2000, which may utilize a singlejoint FIR filter 120 c and thus may be suited for use in scenarios wherethe N transmit chains (e.g. two in the context of FIG. 2 ) containsimilar FIR filters and are thus suitable for joint estimation.Cancelation circuitry 2000 may thus be deployed in each receive chain inorder to estimate and cancel leakage resulting from the transmit chains.

As opposed to separately estimating the tap filter weights for eachtransmit chain, cancelation circuitry 2000 may instead jointly estimatethe tap filter weights for FIR filter circuit 120 c, which may functionequivalently to FIR filter circuit 120 of FIG. 1 in the SISO case.Cancelation circuitry 2000 may apply W_(PA,1) and W_(PA,2) to X₁(t) andX₂(t) to obtain X_(F,1)(t) and X_(F,2)(t), which cancelation circuitry2000 may sum at summation circuit 2002 to obtain X_(FIL)(t). Cancelationcircuitry 2000 may then apply joint FIR filter W_(F) to X_(FIL)(t) toobtain e(t) for subsequent cancelation from y(t) to obtain clean signalz(t).

FIR filter adaptation circuit 126 c of adaptation circuit 124 a/124b/126 c may function equivalently to FIR filter adaptation circuit 126as detailed in FIG. 4 regarding FIR update iteration 214 usingX_(FIL)(t) and z(t) and accordingly calculate the correlation R_(FIL)(t)of X_(FIL)(t) and the cross-correlation β_(FIL)(t) of X_(FIL)(t) andz(t) to identify updates to weights of W_(F). As the FIR filters of eachtransmit chain are assumed to be similar, the updates calculated by FIRfilter adaptation circuit 126 c may able to accurately characterize theleakage path for both transmit chains and accordingly may continue tooffer effective interference cancelation.

As the power amplifiers for each transmit chain are different (and mayhave different input signals and antennas), the non-linearities of eachPA may need to be estimated separately. Adaptation circuit 124 a/124b/126 c may therefore need to adapt both FIR filters W_(PA,1) andW_(PA,2) (one per transmit chain) and thus may contain two PA adaptationcircuits 124 a and 124 b, which may each adapt PA filters W_(PA,1) andW_(PA,2) equivalent to PA filter adaptation circuit 126 as detailed inFIG. 3 regarding PA update iteration 212, i.e. by applying joint FIRfilter W_(F) to filter matrices X₁(t) and X₂(t) to respectively obtainX_(PA,1)(t) and X_(PA,2)(t) and updating W_(PA,1) and W_(PA,2)accordingly. Similar as detailed above regarding alternating betweenupdating the PA and FIR dimensions, adaptation circuit 124 a/124 b/126 cmay alternate between updating joint FIR filter W_(F) and PA filtersW_(PA,1) and W_(PA,2), where adaptation circuit 124 a/124 b/126 c mayfix W_(F) while updating W_(PA,1) and W_(PA,2) for multiple inputsamples before switching to fix W_(PA,1) and W_(PA,2) while updatingW_(F).

As cancelation circuitry 2000 may utilize a single joint FIR filterW_(F) and accompanying FIR filter circuit 120 c, cancelation circuitry2000 may significantly reduce the amount of updates compared to bothcancelation circuitry 1800 and other adaptation schemes, i.e. M+2Kupdates per receive chain (with two transmit chains) compared to 2(M+K)updates and 2MK updates. Cancelation circuitry 2000 may thus be suitablefor deployment in architectures where the FIR filters of each transmitchain are similar. Returning to the context of FIG. 19 , adaptationcircuit 124 a/124 b/126 c may additionally be utilized for adaptationresource sharing between multiple receive chains, where adaptationcircuit 124 a/124 b/126 c may alternate between updating W_(PA,n) andW_(F,n), n=1, . . . , N, for each of the N receive chains, e.g. withswitching based on a predefined number of samples or a convergencecriteria, and thus may enable a significant reduction in hardware area.

In particular for MIMO applications, stability of the cancelation maybecome an issue. Such may be exacerbated in the case of cancelationcircuitry 1800 due to the parallel operation of two adaptation blocks,which may result in the adaptation blocks struggling between one anotherand becoming unbalanced. Additionally, the bilinear architecture mayallow for a greater dynamic range of W_(F) and W_(PA) compared to theconventional ‘Hammerstein’ architecture. While the bilinear algorithmsdetailed herein may perform effectively when W_(F) and W_(PA) arebalanced, ‘peaky’ or ‘noisy’ samples may drive the adaptation out ofreasonable range and thus impair performance. Accordingly, either theFIR weights of W_(F) or the PA weights of W_(PA) may become much largerthan the other dimension; while the resulting mathematical calculationsmay generally produce the same e (t), noisy samples may produceinstability (as one of W_(F) or W_(PA) will be very large).Additionally, fixed-point numerical representations (e.g. in the natureof the bit-level inputs shown in FIG. 6 ) may eventually run intooverflow problems when one of W_(F) or W_(PA) grows to be too large.Accordingly, the update of correlation matrices R_(PA)(t) and R_(F)(t)in 212 b/212 e and 214 b/214 e may be modified in order to introduce aregularization factor, which may counter such imbalances between W_(F)and W_(PA) and ensure that cancelation performance remains stable.Specifically, instead of the correlation updates detailed in Equations(8) and (13), PA filter adaptation circuit 124 and FIR filter adaptationcircuit 126 may update R_(PA)(t) and R_(F)(t) as

R _(PA)(t)=λR _(PA)(t−1)+X _(PA) ^(H)(t)X _(PA)(t)+ϵ_(PA) I  (21)

R _(F) =λR _(F)(t−1)+X _(F) ^(H)(t)X _(F)(t)+ϵ_(F) I  (22)

where ϵ_(PA) and ϵ_(F) are small positive numbers that serve as aregularization factor and I is the identity matrix.

By including regularization factors ϵ_(PA) and ϵ_(F) in the correlationupdate, self-interference cancelation schemes (cancelation circuitry112, cancelation circuitry 1800, and/or cancelation circuitry 2000) maycounter imbalances between the PA and FIR dimension filters.Regularization factors ϵ_(PA) and ϵ_(F) may need to carefully selectedsince the strength thereof will determine the strength of theregularization effect; for example, if ϵ_(PA) or ϵ_(F) is too large,convergence will suffer. Although both ϵ_(PA) and ϵ_(F) are designparameters that may vary on a case-by-case basis, ϵ_(PA) and ϵ_(F) maybe in the order of e.g. 2⁻⁴ or 2⁻⁸ (although such is exemplary and anyvalue could be used) and may need to be selected based on informationabout the received signal and/or the expected strength of theinterference. Although SISO architectures may additionally utilizeEquations (21) and (22), regularization may be more important in MIMOarchitectures. Different regularization factors ϵ_(PA) and ϵ_(F) may bechosen for the cancelation circuitry of each receive chain (includingϵI=0, i.e. a zero matrix that provides no regularization) and may beadjusted in order to ensure update stability.

FIG. 21 shows method 2100 of performing interference cancelation. Asshown in FIG. 21 , method 2100 includes applying a first kerneldimension filter to a first input signal to estimate a first kerneldimension interference signal derived from a first amplifier (2110),applying a second kernel dimension filter to a second input signal toestimate a second kernel dimension interference signal derived from asecond amplifier (2120), applying a joint delay tap dimension filter toa combination of the first kernel dimension interference signal and thesecond kernel dimension interference signal to obtain an estimated jointinterference signal (2130), and removing the estimated jointinterference signal from a received signal to obtain a clean signal(2140).

FIG. 22 shows method 2200 of performing interference cancelation. Asshown in FIG. 22 , method 2200 includes estimating a first interferencesignal produced by a first amplifier with a first kernel dimensionfilter and a first delay tap dimension filter (2210), estimating asecond interference signal produced by a second amplifier with a secondkernel dimension filter and a second delay tap dimension filter (2220),subtracting a combination of the first interference signal and thesecond interference signal from a received signal to obtain a cleansignal (2230), and alternating between a kernel update phase includingupdating the first kernel dimension filter and the second kerneldimension filter and a delay tap update phase including updating thefirst delay tap dimension filter and the second delay tap dimensionfilter (2240).

The terms “user equipment”, “UE”, “mobile terminal”, “user terminal”,etc., may apply to any wireless communication device, including cellularphones, tablets, laptops, personal computers, wearables, multimediaplayback and other handheld electronic devices,consumer/home/office/commercial appliances, vehicles, and any number ofadditional electronic devices capable of wireless communications.

While the above descriptions and connected figures may depict electronicdevice components as separate elements, skilled persons will appreciatethe various possibilities to combine or integrate discrete elements intoa single element. Such may include combining two or more circuits forform a single circuit, mounting two or more circuits onto a common chipor chassis to form an integrated element, executing discrete softwarecomponents on a common processor core, etc. Conversely, skilled personswill recognize the possibility to separate a single element into two ormore discrete elements, such as splitting a single circuit into two ormore separate circuits, separating a chip or chassis into discreteelements originally provided thereon, separating a software componentinto two or more sections and executing each on a separate processorcore, etc.

It is appreciated that implementations of methods detailed herein aredemonstrative in nature, and are thus understood as capable of beingimplemented in a corresponding device. Likewise, it is appreciated thatimplementations of devices detailed herein are understood as capable ofbeing implemented as a corresponding method. It is thus understood thata device corresponding to a method detailed herein may include one ormore components configured to perform each aspect of the related method.

The following examples pertain to further aspects of this disclosure:

Example 1 is a communication circuit arrangement including a firstkernel dimension filter circuit configured to apply a first kerneldimension filter to a first input signal to estimate a first kerneldimension interference signal from a first amplifier, a second kerneldimension filter circuit configured to apply a second kernel dimensionfilter to a second input signal to estimate a second kernel dimensioninterference signal from a second amplifier, a joint delay tap dimensionfilter configured to apply a joint delay tap dimension filter to acombination of the first kernel dimension interference signal and thesecond kernel dimension interference signal to obtain an estimated jointinterference signal, and a cancelation circuit configured to remove theestimated joint interference signal from a received signal to obtain aclean signal.

In Example 2, the subject matter of Example 1 can optionally furtherinclude one or more filter adaptation circuits configured to alternatebetween a kernel update phase during which the one or more filteradaptation circuits update the first kernel dimension filter and secondkernel dimension filter and a delay tap update phase during which theone or more filter adaptation circuits update the joint delay tapdimension filter.

In Example 3, the subject matter of Example 1 or 2 can optionally beconfigured as a radio communication device and further including one ormore receive chains, a first transmit chain including the firstamplifier, a second transmit chain including the second amplifier, andone or more antennas coupled to the one or more receive chains and thefirst transmit chain.

In Example 4, the subject matter of Example 1 or 2 can optionallyinclude wherein the first amplifier is configured to amplify the firstinput signal to form a first amplified signal and the second amplifieris configured to amplify the second input signal to form a secondamplified signal and wherein the one or more antennas are configured totransmit the first amplified signal and the second amplified signal.

In Example 5, the subject matter of Example 3 or 4 can optionallyinclude wherein a first receive chain of the one or more receive chainsis configured to receive the received signal via the one or moreantennas, wherein the estimated joint interference signal includesapproximation of leakage from the first transmit chain and the secondtransmit chain to the first receive chain.

In Example 6, the subject matter of Example 5 can optionally includewherein the one or more filter adaptation circuits are furtherconfigured to update one or more kernel dimension filters or one or moredelay tap dimension filters of at least a second receive chain of theone or more receive chains.

In Example 7, the subject matter of Example 5 or 6 can optionallyinclude wherein the joint delay tap dimension filter is configured toestimate a delay tap response of one or more filters that are common toa leakage path from the first transmit chain and the second transmitchain to the first receive chain.

In Example 8, the subject matter of any one of Examples 3 to 7 canoptionally include wherein the first input signal and the second inputsignal are transmit layers of a Multiple Input Multiple Output (MIMO)communication scheme.

In Example 9, the subject matter of any one of Examples 1 to 8 canoptionally include wherein the one or more filter adaptation circuitsare configured to update the first kernel dimension filter, the secondkernel dimension filter, and the joint delay tap dimension filter inreal-time.

In Example 10, the subject matter of any one of Examples 1 to 9 canoptionally include wherein the one or more filter adaptation circuitsare configured to update the first kernel dimension filter, the secondkernel dimension filter, and the joint delay tap dimension filter byiteratively updating the first kernel dimension filter, the secondkernel dimension filter, and the joint delay tap dimension filter overeach of a plurality of samples of the first input signal and the secondinput signal.

In Example 11, the subject matter of any one of Examples 1 to 10 canoptionally further include a first kernel generation circuit configuredto process the first input signal to derive a first plurality of kernelsignals from the first input signal, each of the first plurality ofkernel signals approximating a non-linear component of a leakage path ofthe first amplifier, wherein the first kernel dimension filter circuitis configured to apply the first kernel dimension filter to the firstinput signal by applying the first kernel dimension filter to the firstplurality of kernel signals.

In Example 12, the subject matter of Example 11 can optionally includewherein each of the first plurality of kernel signals is composed of afirst plurality of delay taps, wherein each weight of the first kerneldimension filter corresponds to a respective one of the first pluralityof kernel signals and each weight of the joint delay tap dimensionfilter corresponds to a respective one of the first plurality of delaytaps.

In Example 13, the subject matter of Example 12 can optionally includewherein the first kernel dimension filter is configured to approximatethe leakage path of the first amplifier over the first plurality ofkernel signals, and wherein the joint delay tap dimension filter isconfigured to approximate the leakage path of the first amplifier overthe first plurality of delay taps.

In Example 14, the subject matter of any one of Examples 1 to 13 canoptionally further include a second kernel generation circuit configuredto process the second input signal to derive a second plurality ofkernel signals from the second input signal, each of the secondplurality of kernel signals approximating a non-linear component of aleakage path of the second amplifier, wherein the second kerneldimension filter circuit is configured to apply the second kerneldimension filter to the second input signal by applying the secondkernel dimension filter to the second plurality of kernel signals.

In Example 15, the subject matter of Example 14 can optionally includewherein each of the second plurality of kernel signals is composed of asecond plurality of delay taps, wherein each weight of the second kerneldimension filter corresponds to a respective one of the second pluralityof kernel signals and each weight of the joint delay tap dimensionfilter corresponds to a respective one of the second plurality of delaytaps.

In Example 16, the subject matter of Example 15 can optionally includewherein the second kernel dimension filter is configured to approximatethe leakage path of the second amplifier over the second plurality ofkernel signals and wherein the joint delay tap dimension filter isconfigured to approximate the leakage path of the second amplifier overthe second plurality of delay taps.

In Example 17, the subject matter of any one of Examples 1 to 16 canoptionally include wherein the first kernel dimension filter, the secondkernel dimension filter, and the joint delay tap dimension filter arevectors.

In Example 18, the subject matter of any one of Examples 1 to 17 canoptionally include wherein the one or more filter adaptation circuitsare configured to update the first kernel dimension filter, the secondkernel dimension filter, and the joint delay tap dimension filter basedon the first input signal, the second input signal, and the cleansignal.

In Example 19, the subject matter of any one of Examples 2 to 18 canoptionally include wherein the one or more filter adaptation circuitsare configured to alternate between the kernel update phase and thedelay tap update phase by comparing the combination of the first kerneldimension interference signal and the second kernel dimensioninterference signal to the clean signal to identify at least one weightof the joint delay tap dimension filter to update during the delay tapupdate phase.

In Example 20, the subject matter of Example 1 can optionally includewherein the one or more filter adaptation circuits are configured tocompare the combination of the first kernel dimension interferencesignal and the second kernel dimension interference signal to the cleansignal to identify at least one weight of the joint delay tap dimensionfilter to update by determining a cross-correlation vector between thecombination of the first kernel dimension interference signal and thesecond kernel dimension interference signal and the clean signal, andidentifying a first weight of the joint delay tap dimension filter toupdate based on the cross-correlation vector.

In Example 21, the subject matter of Example 20 can optionally includewherein the one or more filter adaptation circuits are configured toupdate exclusively the first weight of the joint delay tap dimensionfilter.

In Example 22, the subject matter of Example 20 or 21 can optionallyinclude wherein the one or more filter adaptation circuits areconfigured to update the first weight of the joint delay tap dimensionfilter according to a recursive least squares (RLS) optimization scheme.

In Example 23, the subject matter of Example 22 can optionally includewherein the one or more filter adaptation circuits are configured toupdate exclusively a single bit of the first weight of the joint delaytap dimension filter according to recursive least squares (RLS)dichotomous coordinate descent (DCD) optimization scheme.

In Example 24, the subject matter of any one of Examples 2 to 23 canoptionally include wherein the one or more filter adaptation circuitsare configured to alternate between the kernel update phase and thedelay tap update phase by first applying the joint delay tap dimensionfilter to the first input signal to obtain a first filtered inputsignal, first comparing the first filtered input signal to the cleansignal to identify at least one weight of the first kernel dimensionfilter to update, second applying the joint delay tap dimension filterto the second input signal to obtain a second filtered input signal, andsecond comparing the second filtered input signal to the clean signal toidentify at least one weight of the second kernel dimension filter toupdate, wherein the first applying, first comparing, second applying,and second comparing are performed during the kernel update phase.

In Example 25, the subject matter of Example 1 can optionally includewherein the one or more filter adaptation circuits are configured tocompare the first filtered input signal to the clean signal to identifyat least one weight of the first kernel dimension filter to update bydetermining a cross-correlation vector between the first filtered inputsignal and the clean signal, identifying a first weight of the firstkernel dimension filter to update based on the cross-correlation vector.

In Example 26, the subject matter of Example 25 can optionally includewherein the one or more filter adaptation circuits are configured toupdate exclusively the first weight of the first kernel dimensionfilter.

In Example 27, the subject matter of Example 25 or 26 can optionallyinclude wherein the one or more filter adaptation circuits areconfigured to update the first weight of the first kernel dimensionfilter according to a recursive least squares (RLS) optimization scheme.

In Example 28, the subject matter of Example 27 can optionally includewherein the one or more filter adaptation circuits are configured toupdate exclusively a single bit of the first weight of the first kerneldimension filter according to recursive least squares (RLS) dichotomouscoordinate descent (DCD) optimization scheme.

In Example 29, the subject matter of any one of Examples 1 to 28 canoptionally include wherein the one or more filter adaptation circuitsinclude a first kernel dimension filter adaptation circuit configured toperform the updates to the first kernel dimension filter and furtherinclude a different second kernel dimension adaptation circuitconfigured to perform the updates to the second kernel dimension filter.

In Example 30, the subject matter of any one of Examples 1 to 28 canoptionally include wherein the one or more filter adaptation circuitsinclude a shared kernel dimension update filter compared to alternatebetween updating the first kernel dimension filter and the second kerneldimension filter.

Example 31 is a communication circuit arrangement including a signalpath circuit configured to estimate a first interference signal producedby a first amplifier with a first kernel dimension filter and a firstdelay tap dimension filter and further configured to estimate a secondinterference signal produced by a second amplifier with a second kerneldimension filter and a second delay tap dimension filter, a cancelationcircuit configured to subtract a combination of the first interferencesignal and the second interference signal from a received signal toobtain a clean signal, and one or more filter adaptation circuitsconfigured to alternate between a kernel update phase during which theone or more filter adaptation circuits update the first kernel dimensionfilter and the second kernel dimension filter and a delay update phaseduring which the one or more filter adaptation circuits update the firstdelay tap dimension filter and the second delay tap dimension filter.

In Example 32, the subject matter of Example 31 can optionally beconfigured as a radio communication device and further including one ormore receive chains, a first transmit chain including the firstamplifier, a second transmit chain including the second amplifier, andone or more antennas coupled to the one or more receive chains and thefirst transmit chain.

In Example 33, the subject matter of Example 32 can optionally includewherein a first receive chain of the one or more receive chains isconfigured to receive the received signal via the one or more antennas,wherein the combination of the first interference signal and the secondinterference signal includes approximation of leakage from the firsttransmit chain and the second transmit chain to the first receive chain.

In Example 34, the subject matter of Example 33 can optionally includewherein the one or more filter adaptation circuits are furtherconfigured to update one or more kernel dimension filters or one or moredelay tap dimension filters of at least a second receive chain of theone or more receive chains.

In Example 35, the subject matter of any one of Examples 32 to 34 canoptionally include wherein the first transmit chain and the secondtransmit chain are layers of a Multiple Input Multiple Output (MIMO)communication scheme.

In Example 36, the subject matter of any one of Examples 31 to 35 canoptionally include wherein the first kernel dimension filter and thefirst delay tap dimension filter are configured to approximate a leakagepath from the first amplifier and the second kernel dimension filter andthe second delay tap dimension filter are configured to approximate aleakage path from the second amplifier.

In Example 37, the subject matter of any one of Examples 31 to 36 canoptionally include wherein the one or more filter adaptation circuitsare configured to update the first kernel dimension filter, the firstdelay tap dimension filter, the second kernel dimension filter, and thesecond delay tap dimension filter in real-time.

In Example 38, the subject matter of any one of Examples 31 to 37 canoptionally include wherein the first kernel dimension filter, the secondkernel dimension filter, the first delay tap dimension filter, and thesecond delay tap dimension filter are vectors.

In Example 39, the subject matter of any one of Examples 31 to 38 canoptionally include wherein the signal path circuit is configured toestimate the first interference signal by applying the first kerneldimension filter and the first delay tap dimension filter to a firstinput signal for the first amplifier to obtain the first interferencesignal and configured to estimate the second interference signal byapplying the second kernel dimension filter and the second delay tapdimension filter to a second input signal for the second amplifier toobtain the second interference signal.

In Example 40, the subject matter of Example 39 can optionally includewherein the one or more filter adaptation circuits are configure toupdate the first kernel dimension filter, the first delay tap dimensionfilter, the second kernel dimension filter, and the second delay tapdimension filter by iteratively updating the first kernel dimensionfilter, the first delay tap dimension filter, the second kerneldimension filter, and the second delay tap dimension filter over each ofa plurality of samples of the first input signal and the second inputsignal.

In Example 41, the subject matter of Example 39 or 40 can optionallyfurther include a first kernel generation circuit configured to processthe first input signal to derive a first plurality of kernel signalsfrom the first input signal, each of the first plurality of kernelsignals approximating a non-linear component of a leakage path of thefirst amplifier, wherein the signal path circuit is configured to applythe first kernel dimension filter to the first input signal by applyingthe first kernel dimension filter to the first plurality of kernelsignals.

In Example 42, the subject matter of Example 41 can optionally includewherein each of the first plurality of kernel signals is composed of aplurality of delay taps, wherein each weight of the first kerneldimension filter corresponds to a respective one of the first pluralityof kernel signals and each weight of the first delay tap dimensionfilter corresponds to a respective one of the plurality of delay taps.

In Example 43, the subject matter of Example 42 can optionally includewherein the first kernel dimension filter is configured to approximatethe leakage path of the first amplifier over the first plurality ofkernel signals and the first delay tap dimension filter is configured toapproximate the leakage path of the first amplifier over the firstplurality of delay taps.

In Example 44, the subject matter of any one of Examples 39 to 43 canoptionally further include a second kernel generation circuit configuredto process the second input signal to derive a second plurality ofkernel signals from the second input signal, each of the secondplurality of kernel signals approximating a non-linear component of aleakage path of the second amplifier, wherein the signal path circuit isconfigured to apply the second kernel dimension filter to the secondinput signal by applying the second kernel dimension filter to thesecond plurality of kernel signals.

In Example 45, the subject matter of Example 44 can optionally includewherein each of the second plurality of kernel signals is composed of asecond plurality of delay taps, wherein each weight of the second kerneldimension filter corresponds to a respective one of the second pluralityof kernel signals and each weight of the second delay tap dimensionfilter corresponds to a respective one of the second plurality of delaytaps.

In Example 46, the subject matter of Example 45 can optionally includewherein the second kernel dimension filter is configured to approximatethe leakage path of the second amplifier over the second plurality ofkernel signals and the second delay tap dimension filter is configuredto approximate the leakage path of the second amplifier over the secondplurality of delay taps.

In Example 47, the subject matter of any one of Examples 39 to 46 canoptionally include wherein the one or more filter adaptation circuitsare configured to update the first kernel dimension filter and the firstdelay tap dimension filter based on the first input signal and the cleansignal and configured to update the second kernel dimension filter andthe second delay tap dimension filter based on the second input signaland the clean signal.

In Example 48, the subject matter of any one of Examples 39 to 47 canoptionally include wherein the one or more filter adaptation circuitsare configured to alternate between the kernel update phase and thedelay tap update phase by first applying the first kernel dimensionfilter to the first input signal to obtain a first filtered inputsignal, first comparing the first filtered input signal to the cleansignal to identify at least one weight of the first delay tap dimensionfilter to update, second applying the second kernel dimension filter tothe second input signal to obtain a second filtered input signal, andsecond comparing the second filtered input signal to the clean signal toidentify at least one weight of the second delay tap dimension filter toupdate, wherein the first applying, first comparing, second applying,and second comparing are performed during the delay tap update phase.

In Example 49, the subject matter of Example 48 can optionally includewherein the one or more filter adaptation circuits are configured tocompare the first filtered input signal to the clean signal to identifythe at least one weight of the first delay tap dimension filter toupdate by determining a cross-correlation vector between the firstfiltered input signal and the clean signal, identifying a first weightof the first delay tap dimension filter to update based on thecross-correlation vector.

In Example 50, the subject matter of Example 49 can optionally includewherein the one or more filter adaptation circuits are configured toupdate exclusively the first weight of the first delay tap dimensionfilter.

In Example 51, the subject matter of Example 49 or 50 can optionallyinclude wherein the one or more filter adaptation circuits areconfigured to update the first weight of the first delay tap dimensionfilter according to a recursive least squares (RLS) optimization scheme.

In Example 52, the subject matter of Example 51 can optionally includewherein the one or more filter adaptation circuits are configured toupdate the first weight of the first delay tap dimension filteraccording to a recursive least square (RLS) dichotomous coordinatedescent (DCD) optimization scheme.

In Example 53, the subject matter of any one of Examples 48 to 52 canoptionally include wherein the one or more filter adaptation circuitsinclude a first delay tap dimension filter adaptation circuit configuredto perform the updates to the first delay tap dimension filter andfurther include a different second delay tap dimension adaptationcircuit configured to perform the updates to the second delay tapdimension filter.

In Example 54, the subject matter of any one of Examples 48 to 52 canoptionally include wherein the one or more filter adaptation circuitsinclude a shared delay tap dimension update filter compared to alternatebetween updating the first delay tap dimension filter and the seconddelay tap dimension filter

In Example 55, the subject matter of any one of Examples 39 to 52 canoptionally include wherein the one or more filter adaptation circuitsare configured to alternate between the kernel update phase and thedelay tap update phase by first applying the first delay tap dimensionfilter to the first input signal to obtain a first filtered inputsignal, first comparing the first filtered input signal to the cleansignal to identify at least one weight of the first kernel dimensionfilter to update, second applying the second delay dimension filter tothe second input signal to obtain a second filtered input signal, andsecond comparing the second filtered input signal to the clean signal toidentify at least one weight of the second kernel dimension filter toupdate, wherein the first applying, first comparing, second applying,and second comparing are performed during the kernel update phase.

In Example 56, the subject matter of Example 55 can optionally includewherein the one or more filter adaptation circuits are configured tocompare the first filtered input signal to the clean signal to identifyat least one weight of the first kernel dimension filter to update bydetermining a cross-correlation vector between the first filtered inputsignal and the clean signal, identifying a first weight of the firstkernel dimension filter to update based on the cross-correlation vector.

In Example 57, the subject matter of Example 56 can optionally includewherein the one or more filter adaptation circuits are configured toupdate exclusively the first weight of the first kernel dimensionfilter.

In Example 58, the subject matter of Example 56 or 57 can optionallyinclude wherein the one or more filter adaptation circuits areconfigured to update the first weight of the first kernel dimensionfilter according to a recursive least squares (RLS) optimization scheme.

In Example 59, the subject matter of Example 58 can optionally includewherein the one or more filter adaptation circuits are configured toupdate exclusively a single bit of the first weight of the first kerneldimension filter according to recursive least squares (RLS) dichotomouscoordinate descent (DCD) optimization scheme.

In Example 60, the subject matter of any one of Examples 55 to 59 canoptionally include wherein the one or more filter adaptation circuitsinclude a first kernel dimension filter adaptation circuit configured toperform the updates to the first kernel dimension filter and furtherinclude a different second kernel dimension adaptation circuitconfigured to perform the updates to the second kernel dimension filter.

In Example 61, the subject matter of any one of Examples 55 to 59 canoptionally include wherein the one or more filter adaptation circuitsinclude a shared kernel dimension update filter compared to alternatebetween updating the first kernel dimension filter and the second kerneldimension filter.

Example 62 is a method of performing interference cancelation includingapplying a first kernel dimension filter to a first input signal toestimate a first kernel dimension interference signal derived from afirst amplifier, applying a second kernel dimension filter to a secondinput signal to estimate a second kernel dimension interference signalderived from a second amplifier, applying a joint delay tap dimensionfilter to a combination of the first kernel dimension interferencesignal and the second kernel dimension interference signal to obtain anestimated joint interference signal, and removing the estimated jointinterference signal from a received signal to obtain a clean signal.

In Example 63, the subject matter of Example 62 can optionally furtherinclude alternating between a kernel update phase including updating thefirst kernel dimension filter and the second kernel dimension filter anda delay tap update phase including updating the joint delay tapdimension filter.

In Example 64, the subject matter of Example 62 or 63 can optionallyfurther include amplifying the first input signal with the firstamplifier to form a first amplified signal, amplifying the second inputsignal with the second amplifier to form a second amplified signal, andwirelessly transmitting the first amplified signal and the secondamplified signal.

In Example 65, the subject matter of Example 64 can optionally furtherinclude receiving the received signal at a receive chain, where theestimated joint interference signal includes approximation of leakagefrom the first amplifier and the second amplifier to the receive chain.

In Example 66, the subject matter of Example 65 can optionally includewherein the joint delay tap estimation filter estimates a delay tapresponse of one or more filters that are common to a leakage path fromboth the first amplifier and the second amplifier to the receive chain.

In Example 67, the subject matter of any one of Examples 64 to 66 canoptionally include wherein the first input signal and the second inputsignal are transmit layers of a Multiple Input Multiple Output (MIMO)communication scheme.

In Example 68, the subject matter of any one of Examples 63 to 67 canoptionally include wherein the kernel update phase and the delay tapupdate phase include updating the first kernel dimension filter, thesecond kernel dimension filter, and the joint delay tap dimension filterin real-time.

In Example 69, the subject matter of any one of Examples 63 to 68 canoptionally include wherein the kernel update phase and the delay tapupdate phase include iteratively updating the first kernel dimensionfilter, the second kernel dimension filter, and the joint delay tapdimension filter over each of a plurality of samples of the first inputsignal and the second input signal.

In Example 70, the subject matter of any one of Examples 62 to 69 canoptionally further include processing the first input signal to derive afirst plurality of kernel signals from the first input signal, each ofthe first plurality of kernel signals approximating a non-linearcomponent of a leakage path of the first amplifier, and wherein applyingthe first kernel dimension filter to the first input signal to estimatethe first kernel dimension interference signal includes applying thefirst kernel dimension filter to the first plurality of kernel signals.

In Example 71, the subject matter of Example 70 can optionally includewherein each of the first plurality of kernel signals is composed of afirst plurality of delay taps, wherein each weight of the first kerneldimension filter corresponds to a respective one of the first pluralityof kernel signals and each weight of the joint delay tap dimensionfilter corresponds to a respective one of the first plurality of delaytaps.

In Example 72, the subject matter of Example 71 can optionally includewherein the first kernel dimension filter is configured to approximatethe leakage path of the first amplifier over the first plurality ofkernel signals and the joint delay tap dimension filter is configured toapproximate the leakage path of the first amplifier over the firstplurality of delay taps.

In Example 73, the subject matter of any one of Examples 62 to 72 canoptionally further include processing the second input signal to derivea second plurality of kernel signals from the second input signal, eachof the second plurality of kernel signals approximating a non-linearcomponent of a leakage path of the second amplifier, and whereinapplying the second kernel dimension filter to the second input signalto estimate the second kernel dimension interference signal includesapplying the second kernel dimension filter to the second plurality ofkernel signals.

In Example 74, the subject matter of Example 73 can optionally includewherein each of the second plurality of kernel signals is composed of asecond plurality of delay taps, wherein each weight of the second kerneldimension filter corresponds to a respective one of the second pluralityof kernel signals and each weight of the joint delay tap dimensionfilter corresponds to a respective one of the second plurality of delaytaps.

In Example 75, the subject matter of Example 74 can optionally includewherein the second kernel dimension filter is configured to approximatethe leakage path of the second amplifier over the second plurality ofkernel signals and the joint delay tap dimension filter is configured toapproximate the leakage path of the second amplifier over the secondplurality of delay taps.

The method of any one of Examples 62 to 75, wherein the first kerneldimension filter, the second kernel dimension filter, and the jointdelay tap dimension filter are vectors.

In Example 77, the subject matter of any one of Examples 63 to 76 canoptionally include wherein the kernel update phase and the delay tapupdate phase include updating the first kernel dimension filter, thesecond kernel dimension filter, and the joint delay tap dimension filterbased on the first input signal, the second input signal, and the cleansignal.

In Example 78, the subject matter of any one of Examples 63 to 77 canoptionally include wherein the delay tap update phase includes updatingthe joint delay tap dimension filter by comparing the combination of thefirst kernel dimension interference signal and the second kerneldimension interference signal to the clean signal to identify at leastone weight of the joint delay tap dimension filter to update.

In Example 79, the subject matter of Example 78 can optionally includewherein comparing the combination of the first kernel dimensioninterference signal and the second kernel dimension interference signalto the clean signal to identify the at least one weight of the jointdelay tap dimension filter to update includes determining across-correlation vector between the combination of the first kerneldimension interference signal and the second kernel dimensioninterference signal and the clean signal, and identifying a first weightof the joint delay tap dimension filter to update based on thecross-correlation vector.

In Example 80, the subject matter of Example 79 can optionally includewherein identifying the first weight of the joint delay tap dimensionfilter to update based on the cross-correlation vector includes updatingexclusively the first weight of the joint delay tap dimension filter.

In Example 81, the subject matter of Example 79 can optionally includewherein identifying the first weight of the joint delay tap dimensionfilter to update based on the cross-correlation vector includes updatingthe first weight of the joint delay tap dimension filter according to arecursive least squares (RLS) optimization scheme.

In Example 82, the subject matter of Example 81 can optionally includewherein identifying the first weight of the joint delay tap dimensionfilter to update based on the cross-correlation vector includes updatingexclusively a single bit of the first weight of the joint delay tapdimension filter according to recursive least squares (RLS) dichotomouscoordinate descent (DCD) optimization scheme.

In Example 83, the subject matter of any one of Examples 63 to 82 canoptionally include wherein the kernel update phase includes applying thejoint delay tap dimension filter to the first input signal to obtain afirst filtered input signal, comparing the first filtered input signalto the clean signal to identify at least one weight of the first kerneldimension filter to update, applying the joint delay tap dimensionfilter to the second input signal to obtain a second filtered inputsignal, and comparing the second filtered input signal to the cleansignal to identify at least one weight of the second kernel dimensionfilter to update.

In Example 84, the subject matter of Example 83 can optionally includewherein comparing the first filtered input signal to the clean signal toidentify the at least one weight of the first kernel dimension filter toupdate includes determining a cross-correlation vector between the firstfiltered input signal and the clean signal, identifying a first weightof the first kernel dimension filter to update based on thecross-correlation vector.

In Example 85, the subject matter of Example 84 can optionally includewherein identifying the first weight of the first kernel dimensionfilter to update based on the cross-correlation vector includes updatingexclusively the first weight of the first kernel dimension filter.

In Example 86, the subject matter of Example 84 can optionally includewherein identifying the first weight of the first kernel dimensionfilter to update based on the cross-correlation vector includes updatingthe first weight of the first kernel dimension filter according to arecursive least squares (RLS) optimization scheme.

In Example 87, the subject matter of Example 84 can optionally includewherein identifying the first weight of the first kernel dimensionfilter to update based on the cross-correlation vector includes updatingexclusively a single bit of the first weight of the first kerneldimension filter according to a recursive least squares (RLS)dichotomous coordinate descent (DCD) optimization scheme.

Example 88 is a method of performing interference cancelation includingestimating a first interference signal produced by a first amplifierwith a first kernel dimension filter and a first delay tap dimensionfilter, estimating a second interference signal produced by a secondamplifier with a second kernel dimension filter and a second delay tapdimension filter, subtracting a combination of the first interferencesignal and the second interference signal from a received signal toobtain a clean signal, and alternating between a kernel update phaseincluding updating the first kernel dimension filter and the secondkernel dimension filter and a delay tap update phase including updatingthe first delay tap dimension filter and the second delay tap dimensionfilter.

In Example 89, the subject matter of Example 88 can optionally furtherinclude amplifying a first input signal with the first amplifier,amplifying a second input signal with the second amplifier, andwirelessly transmitting the amplified first input signal and theamplified second input signal.

In Example 90, the subject matter of Example 89 can optionally furtherinclude receiving the received signal at a receive chain, wherein thecombination of the first interference signal and the second interferencesignal includes approximation of leakage from the first power amplifierand the second power amplifier to the receive chain.

In Example 91, the subject matter of Example 89 can optionally includewherein the first input signal and the second input signal are transmitlayers of a Multiple Input Multiple Output (MIMO) communication scheme.

In Example 92, the subject matter of any one of Examples 88 to 91 canoptionally include wherein the first kernel dimension filter and thefirst delay tap dimension filter are configured to approximate a leakagepath from the first amplifier and the second kernel dimension filter andthe second delay tap dimension filter are configured to approximate aleakage path from the second amplifier.

In Example 93, the subject matter of any one of Examples 88 to 92 canoptionally include wherein the kernel update phase and the delay tapupdate phase include updating the first kernel dimension filter, thesecond kernel dimension filter, the first delay tap dimension filter,and the second delay tap dimension filter in real-time.

In Example 94, the subject matter of any one of Examples 88 to 92 canoptionally include wherein the first kernel dimension filter, the secondkernel dimension filter, the first delay tap dimension filter, and thesecond delay tap dimension filter are vectors.

In Example 95, the subject matter of any one of Examples 88 to 94 canoptionally include wherein estimating the first interference signalproduced by the first amplifier with the first kernel dimension filterand the first delay tap dimension filter includes applying the firstkernel dimension filter and the first delay tap dimension filter to afirst input signal for the first amplifier to obtain the firstinterference signal, and wherein estimating the second interferencesignal produced by the second amplifier with the second kernel dimensionfilter and the second kernel dimension filter includes applying thefirst kernel dimension filter and the second kernel dimension filter toa second input signal for the second amplifier to obtain the secondinterference signal.

In Example 96, the subject matter of Example 95 can optionally includewherein the kernel update phase and the delay tap update phase includeupdating the first kernel dimension filter, the first delay tapdimension filter, the second kernel dimension filter, and the seconddelay tap dimension filter by iteratively updating the first kerneldimension filter, the first delay tap dimension filter, the secondkernel dimension filter, and the second delay tap dimension filter overeach of a plurality of samples of the first input signal and the secondinput signal.

In Example 97, the subject matter of any one of Examples, furtherincluding can optionally include the first input signal to derive afirst plurality of kernel signals from the first input signal, each ofthe first plurality of kernel signals approximating a non-linearcomponent of a leakage path of the first amplifier, and wherein applyingthe first kernel dimension filter and the first delay tap dimensionfilter to the first input signal for the first amplifier to obtain thefirst interference signal includes applying the first kernel dimensionfilter to the first plurality of kernel signals.

In Example 98, the subject matter of Example 97 can optionally includewherein each of the first plurality of kernel signals is composed of afirst plurality of delay taps, wherein each weight of the first kerneldimension filter corresponds to a respective one of the first pluralityof kernel signals and each weight of the first delay tap dimensionfilter corresponds to a respective one of the first plurality of delaytaps.

In Example 99, the subject matter of Example 98 can optionally includewherein the first kernel dimension filter is configured to approximatethe leakage path of the first amplifier over the first plurality ofkernel signals and the first delay tap dimension filter is configured toapproximate the leakage path of the first amplifier over the firstplurality of delay taps.

In Example 100, the subject matter of any one of Examples 95 to 99 canoptionally further include processing the second input signal to derivea second plurality of kernel signals from the second input signal, eachof the second plurality of kernel signals approximating a non-linearcomponent of a leakage path of the second amplifier, and whereinapplying the second kernel dimension filter and the second delay tapdimension filter to the second input signal for the second amplifier toobtain the second interference signal includes applying the secondkernel dimension filter to the second plurality of kernel signals.

In Example 101, the subject matter of Example 100 can optionally includewherein each of the second plurality of kernel signals is composed of asecond plurality of delay taps, wherein each weight of the second kerneldimension filter corresponds to a respective one of the second pluralityof kernel signals and each weight of the second delay tap dimensionfilter corresponds to a respective one of the second plurality of delaytaps.

In Example 102, the subject matter of Example 98 can optionally includewherein the second kernel dimension filter is configured to approximatethe leakage path of the second amplifier over the second plurality ofkernel signals and the second delay tap dimension filter is configuredto approximate the leakage path of the first amplifier over the secondplurality of delay taps.

In Example 103, the subject matter of any one of Examples 95 to 102 canoptionally include wherein the kernel update phase and the delay tapupdate phase include updating the first kernel dimension filter and thefirst delay tap dimension filter based on the first input signal and theclean signal and updating the second kernel dimension filter and thesecond kernel dimension filter based on the second input signal and theclean signal.

In Example 104, the subject matter of any one of Examples 95 to 103 canoptionally include wherein the delay tap update phase includes applyingthe first kernel dimension filter to the first input signal to obtain afirst filtered input signal, comparing the first filtered input signalto the clean signal to identify at least one weight of the first delaytap dimension filter to update, applying the second kernel dimensionfilter to the second input signal to obtain a second filtered inputsignal, and comparing the second filtered input signal to the cleansignal to identify at least one weight of the second delay tap dimensionfilter to update.

In Example 105, the subject matter of Example 104 can optionally includewherein comparing the first filtered input signal to the clean signal toidentify the at least one weight of the first delay tap dimension filterto update includes determining a cross-correlation vector between thefirst filtered input signal and the clean signal, identifying a firstweight of the first delay tap dimension filter to update based on thecross-correlation vector.

In Example 106, the subject matter of Example 105 can optionally includewherein identifying the first weight of the first delay tap dimensionfilter to update based on the cross-correlation vector includes updatingexclusively the first weight of the first delay tap dimension filter.

In Example 107, the subject matter of Example 105 or 106 can optionallyinclude wherein identifying the first weight of the first delay tapdimension filter to update based on the cross-correlation vectorincludes updating the first weight of the first delay tap dimensionfilter according to a recursive least squares (RLS) optimization scheme.

In Example 108, the subject matter of Example 105 or 106 can optionallyinclude wherein identifying the first weight of the first delay tapdimension filter to update based on the cross-correlation vectorincludes updating the first weight of the first delay tap dimensionfilter according to a recursive least square (RLS) dichotomouscoordinate descent (DCD) optimization scheme.

In Example 109, the subject matter of any one of Examples 95 to 108 canoptionally include wherein the kernel update phase includes applying thefirst delay tap dimension filter to the first input signal to obtain afirst filtered input signal, comparing the first filtered input signalto the clean signal to identify at least one weight of the first kerneldimension filter to update, applying the second delay dimension filterto the second input signal to obtain a second filtered input signal, andcomparing the second filtered input signal to the clean signal toidentify at least one weight of the second kernel dimension filter toupdate.

In Example 110, the subject matter of Example 109 can optionally includewherein comparing the first filtered input signal to the clean signal toidentify the at least one weight of the first kernel dimension filter toupdate includes determining a cross-correlation vector between the firstfiltered input signal and the clean signal, identifying a first weightof the first kernel dimension filter to update based on thecross-correlation vector.

In Example 111, the subject matter of Example 110 can optionally includewherein identifying the first weight of the first kernel dimensionfilter to update based on the cross-correlation vector includes updatingexclusively the first weight of the first kernel dimension filter.

In Example 112, the subject matter of Example 110 or 111 can optionallyinclude wherein identifying the first weight of the first kerneldimension filter to update based on the cross-correlation vectorincludes updating the first weight of the first kernel dimension filteraccording to a recursive least squares (RLS) optimization scheme.

In Example 113, the subject matter of Example 110 or 111 can optionallyinclude wherein identifying the first weight of the first kerneldimension filter to update based on the cross-correlation vectorincludes updating the first weight of the first kernel dimension filteraccording to a recursive least square (RLS) dichotomous coordinatedescent (DCD) optimization scheme.

Example 114 is a method of performing interference cancelation includingseparately applying a kernel dimension filter and a delay tap dimensionfilter to an input signal for an amplifier to obtain an estimatedinterference signal, subtracting the estimated interference signal froma received signal to obtain a clean signal, and alternating betweenupdating the kernel dimension filter and updating the delay tapdimension filter using the clean signal.

In Example 115, the subject matter of Example 114 can optionally includewherein alternating between updating the kernel dimension filter andupdating the delay tap dimension filter using the clean signal includesupdating the kernel dimension filter in real-time over a first pluralityof digital time samples of the input signal and updating the delay tapdimension filter in real-time over a second plurality of digital timesamples of the input signal.

In Example 116, the subject matter of Example 114 can optionally includewherein the input signal includes a plurality of digital time samples,and wherein alternating between updating the kernel dimension filter andupdating the delay tap dimension filter using the clean signal includesupdating the kernel dimension filter or the delay tap dimension filterover each of the plurality of digital time samples.

In Example 117, the subject matter of Example 114 can optionally includewherein separately applying the kernel dimension filter and the delaytap dimension filter to the input signal for the amplifier to obtain theestimated interference signal includes processing the input signal toderive a plurality of kernel signals from the input signal, wherein eachof the plurality of kernel signals approximates a non-linear componentof a response of the amplifier, and separately applying the kerneldimension filter and the delay tap dimension filter to the plurality ofkernel signals to obtain the estimated interference signal.

In Example 118, the subject matter of Example 117 can optionally includewherein each of the plurality of kernel signals is composed of aplurality of delay taps, wherein each weight of the kernel dimensionfilter corresponds to a respective one of the plurality of kernelsignals and each weight of the delay tap dimension filter corresponds toa respective one of the plurality of delay taps.

In Example 119, the subject matter of Example 118 can optionally includewherein the number of plurality of kernel signals is configurable or thenumber of plurality of delay taps is configurable.

In Example 120, the subject matter of Example 118 can optionally includewherein the kernel dimension filter approximates the response of theamplifier over the plurality of kernel signals and the delay tapdimension filter approximates the response of the amplifier over theplurality of delay taps.

In Example 121, the subject matter of any one of Examples 114 to 120 canoptionally include wherein the kernel dimension filter and the delay tapdimension filter are vectors.

In Example 122, the subject matter of any one of Examples 114 to 120 canoptionally further include amplifying the input signal with theamplifier and transmitting the amplified input signal with a radioantenna.

In Example 123, the subject matter of Example 120 can optionally furtherinclude receiving the received signal with the radio antenna, whereinthe estimated interference signal approximates leakage from theamplified input signal that is contained in the received signal.

In Example 124, the subject matter of any one of Examples 114 to 123 canoptionally include wherein alternating between updating the kerneldimension filter and updating the delay tap dimension filter includesupdating the kernel dimension filter and the delay tap dimension filterbased on the plurality of kernel signals and the clean signal.

In Example 125, the subject matter of any one of Examples 117 to 123 canoptionally include wherein alternating between updating the kerneldimension filter and updating the delay tap dimension filter includesselecting between the kernel dimension filter and the delay tapdimension filter to identify a current filter to update and a fixedfilter to hold constant, applying the fixed filter to the plurality ofkernel signals to obtain a decoupled input signal, and comparing thedecoupled input signal to the clean signal to identify at least oneweight of the current filter to update.

In Example 126, the subject matter of Example 125 can optionally includewherein comparing the decoupled input signal to the clean signal toidentify the at least one weight of the current filter to updateincludes determining a cross-correlation vector between the decoupledinput signal and the clean signal, identifying a first weight of thecurrent filter to update based on the cross-correlation vector, andexclusively updating the first weight of the current filter.

In Example 127, the subject matter of Example 126 can optionally includewherein identifying the first weight of the current filter to updatebased on the cross-correlation vector includes identifying amaximum-valued element of the cross-correlation vector, and identifyingthe weight of the current filter with a corresponding element index tothe maximum-valued element of the cross-correlation vector as the firstweight.

In Example 128, the subject matter of Example 127 can optionally includewherein identifying the maximum-valued element of the cross-correlationvector includes identifying the element of the cross-correlation vectorwith the largest real component or the largest imaginary component asthe maximum-valued element.

In Example 129, the subject matter of Example 125 can optionally includewherein comparing the decoupled input signal to the clean signal toidentify the at least one weight of the current filter to updateincludes determining a cross-correlation vector between the decoupledinput signal and the clean signal, and updating the at least one weightof the current filter to reduce a magnitude of the cross-correlationvector.

In Example 130, the subject matter of Example 129 can optionally includewherein updating the at least one weight of the current filter to reducethe magnitude of the cross-correlation vector includes updating the atleast one weight of the current filter to reduce the magnitude of thecross-correlation vector according to a coordinate descent optimizationscheme.

In Example 131, the subject matter of Example 129 can optionally includewherein updating the at least one weight of the current filter to reducethe magnitude of the cross-correlation vector includes updating the atleast one weight of the current filter to reduce the magnitude of thecross-correlation vector according to a recursive least squaresoptimization scheme.

In Example 132, the subject matter of Example 129 can optionally includewherein updating the at least one weight of the current filter to reducethe magnitude of the cross-correlation vector includes updating the atleast one weight of the current filter to reduce the magnitude of thecross-correlation vector according to a recursive least squares (RLS)dichotomous coordinate descent (DCD) optimization scheme.

In Example 133, the subject matter of Example 129 can optionally includewherein updating the at least one weight of the current filter to reducethe magnitude of the cross-correlation vector includes exclusivelyinverting a single bit of the first weight to reduce the magnitude ofthe cross-correlation vector.

In Example 134, the subject matter of Example 133 can optionally includewherein updating the at least one weight of the current filter to reducethe magnitude of the cross-correlation vector further includesevaluating one or more candidate bit inversions of the first weight toidentify which of the one or more candidate bit inversions is closest toa predefined numerical difference, and identifying the single bitaccording to which of the one or more candidate bit inversions isclosest to the predefined numerical difference.

In Example 135, the subject matter of Example 133 can optionally includewherein exclusively inverting the single bit of the first weight toreduce the magnitude of the cross-correlation vector includes invertingthe single bit of the first weight according to a dichotomous coordinatedescent optimization scheme.

In Example 136, the subject matter of Example 125 can optionally includewherein selecting between the kernel dimension filter and the delay tapdimension filter to identify the current filter to update and the fixedfilter to hold constant includes selecting the kernel dimension filteras the current filter and the delay tap dimension filter as the fixedfilter, and wherein applying the fixed filter to the plurality of kernelsignals to obtain the decoupled input signal includes applying previousdelay taps of the delay tap dimension filter to previous delay taps ofthe plurality of kernel signals during a preprocessing stage that occursbefore receiving a most recent delay tap of the plurality of kernelsignals, and after receiving the most recent delay tap of the pluralityof kernel signals, applying a most recent delay tap of the delay tapdimension filter to the most recent delay tap of the plurality of kernelsignals.

In Example 137, the subject matter of Example 136 can optionally furtherinclude performing the preprocessing stage during hidden clock cyclesthat occur before the most recent delay tap of the plurality of kernelsignals is obtained.

In Example 138, the subject matter of Example 125 can optionally includewherein selecting between the kernel dimension filter and the delay tapdimension filter to identify the current filter to update and the fixedfilter to hold constant includes selecting the delay tap dimensionfilter as the current filter and the kernel dimension filter as thefixed filter, and wherein applying the fixed filter to the plurality ofkernel signals to obtain the decoupled input signal includes exclusivelyapplying the kernel dimension filter to samples of the plurality ofkernel signals corresponding to a single delay tap to obtain a firstelement of the decoupled input signal.

In Example 139, the subject matter of Example 138 can optionally includewherein the remaining elements of the decoupled input signal aretime-delayed weighted versions of the first element of the decoupledinput signal.

In Example 140, the subject matter of any one of Examples 117 to 135 canoptionally include wherein alternating between updating the kerneldimension filter and updating the delay tap dimension filter includesselecting between the kernel dimension filter and the delay tapdimension filter to identify a current filter to update and a fixedfilter to hold constant, applying the fixed filter to the plurality ofkernel signals to obtain a decoupled input signal, determining across-correlation vector between the decoupled input signal and theclean signal and determining a correlation matrix of the decoupled inputsignal, and updating at least one weight of the current filter based onthe cross-correlation vector and the correlation matrix.

In Example 141, the subject matter of Example 140 can optionally includewherein determining the cross-correlation vector between the decoupledinput signal and the clean signal includes determining some elements ofthe cross-correlation vector during a first clock cycle with firstcalculation circuitry and determining other elements of thecross-correlation vector during a second clock cycle with the same firstcalculation circuitry, or determining some elements of the correlationmatrix during a third clock cycle with second calculation circuitry anddetermining other elements of the correlation matrix during a secondclock cycle with the same second calculation circuitry.

In Example 142, the subject matter of Example 140 can optionally includewherein selecting between the kernel dimension filter and the delay tapdimension filter to identify the current filter to update and the fixedfilter to hold constant includes selecting the kernel dimension filteras the current filter and the delay tap dimension filter as the fixedfilter, and wherein determining the cross-correlation vector between thedecoupled input signal and the clean signal and determining thecorrelation matrix of the decoupled input signal includes exclusivelydetermining the upper-triangle elements of the correlation matrix.

In Example 43, the subject matter of Example 142 can optionally includewherein the correlation matrix is a Hermitian matrix.

In Example 144, the subject matter of Example 140 can optionally includewherein selecting between the kernel dimension filter and the delay tapdimension filter to identify the current filter to update and the fixedfilter to hold constant includes selecting the delay tap dimensionfilter as the current filter and the kernel dimension filter as thefixed filter, and wherein determining the cross-correlation vectorbetween the decoupled input signal and the clean signal and determiningthe correlation matrix of the decoupled input signal includesexclusively determining a single row of the correlation matrix.

In Example 145, the subject matter of Example 144 can optionally includewherein a plurality of rows including the single row of the correlationmatrix are statistically similar.

In Example 146, the subject matter of any one of Examples 114 to 139 canoptionally include wherein alternating between updating the kerneldimension filter and updating the delay tap dimension filter includesusing shared circuitry to update the kernel dimension filter andre-using the same shared circuitry to update the delay tap dimensionfilter.

In Example 147, the subject matter of any one of Examples 114 to 139 canoptionally include wherein alternating between updating the kerneldimension filter and updating the delay tap dimension filter includesusing shared circuitry to update the kernel dimension filter andre-using the same shared circuitry to update the delay tap dimensionfilter according to a pipeline clock schedule.

In Example 148, the subject matter of Example 147 can optionally includewherein alternating between updating the kernel dimension filter andupdating the delay tap dimension filter includes updating the kerneldimension filter at one or more first times and updating the delay tapdimension at one or more different second times.

Example 149 is a communication circuitry arrangement configured toperform the method of any one of Examples 114 to 148.

In Example 150, the subject matter of Example 149 can optionally beconfigured as a radio communication device.

Example 151 is a non-transitory computer readable medium storinginstructions that when executed by a controller of a radio communicationdevice direct the radio communication device to perform the method ofany one of Examples 114 to 148.

Example 152 is a method of performing interference cancelation includingobtaining one or more subsignals derived from an input signal for anamplifier, each of the one or more subsignals representing a non-linearcomponent of an amplifier response and composed of a plurality of delaytaps, separately applying a first filter and a second filter to the oneor more subsignals to obtain an estimated interference signal, whereinthe first filter approximates the amplifier response over the one ormore subsignals and the second filter approximates the amplifierresponse over the plurality of delay taps, subtracting the estimatedinterference signal from a received signal to obtain a clean signal, andalternating between updating the first filter and updating the secondfilter using the clean signal.

In Example 153, the subject matter of Example 152 can optionally includewherein alternating between updating the first filter and updating thesecond filter using the clean signal includes updating the first filterin real-time over a first plurality of digital time samples of the inputsignal and updating second first filter in real-time over a secondplurality of digital time samples of the input signal.

In Example 154, the subject matter of Example 152 can optionally includewherein the input signal includes a plurality of digital time samples,and wherein alternating between updating the first filter and updatingthe second filter using the clean signal includes updating the firstfilter or the second filter over each of the plurality of digital timesamples.

In Example 155, the subject matter of Example 152 can optionally includewherein each of the one or more subsignals correspond to a kernel of theamplifier.

In Example 156, the subject matter of Example 152 or 155 can optionallyinclude wherein the first filter and the second filter are vectors.

In Example 157, the subject matter of any one of Examples 152 to 156 canoptionally include wherein each weight of the first filter correspondsto a respective one of the one or more subsignals and each weight of thesecond filter corresponds to a respective delay tap of the plurality ofdelay taps.

In Example 158, the subject matter of any one of Examples 152 to 157 canoptionally include wherein the number of one or more subsignals isconfigurable the number of the plurality of delay taps is configurable.

In Example 159, the subject matter of any one of Examples 152 to 158 canoptionally further include amplifying the input signal with theamplifier and transmitting the amplified input signal with a radioantenna.

In Example 160, the subject matter of Example 159 can optionally furtherinclude receiving the received signal with the radio antenna, whereinthe estimated interference signal approximates leakage from theamplified input signal that is contains in the received signal.

In Example 161, the subject matter of any one of Examples 152 to 160 canoptionally include wherein alternating between updating the first filterand updating the second filter includes updating the first filter andthe second filter based on the one or more subsignals and the cleansignal.

In Example 162, the subject matter of any one of Examples 152 to 160 canoptionally include wherein alternating between updating the first filterand updating the second filter includes selecting between the firstfilter and the second filter to identify a current filter to update anda fixed filter to hold constant, applying the fixed filter to the one ormore subsignals to obtain a decoupled input signal, and comparing thedecoupled input signal to the clean signal to identify at least oneweight of the current filter to update.

In Example 163, the subject matter of Example 162 can optionally includewherein comparing the decoupled input signal to the clean signal toidentify the at least one weight of the current filter to updateincludes determining a cross-correlation vector between the decoupledinput signal and the clean signal, identifying a first weight of thecurrent filter to update based on the cross-correlation vector, andexclusively updating the first weight of the current filter.

In Example 164, the subject matter of Example 163 can optionally includewherein identifying the first weight of the current filter to updatebased on the cross-correlation vector includes identifying amaximum-valued element of the cross-correlation vector, and identifyingthe weight of the current filter with a corresponding element index tothe maximum-valued element of the cross-correlation vector as the firstweight.

In Example 165, the subject matter of Example 164 can optionally includewherein identifying the maximum-valued element of the cross-correlationvector includes identifying the element of the cross-correlation vectorwith the largest real component or the largest imaginary component asthe maximum-valued element.

In Example 166, the subject matter of Example 162 can optionally includewherein comparing the decoupled input signal to the clean signal toidentify the at least one weight of the current filter to updateincludes determining a cross-correlation vector between the decoupledinput signal and the clean signal, and updating the at least one weightof the current filter to reduce a magnitude of the cross-correlationvector.

In Example 167, the subject matter of Example 166 can optionally includewherein updating the at least one weight of the current filter to reducea magnitude of the cross-correlation vector includes updating the atleast one weight of the current filter to reduce a magnitude of thecross-correlation vector according to a coordinate descent optimizationscheme.

In Example 168, the subject matter of Example 166 can optionally includewherein updating the at least one weight of the current filter to reducea magnitude of the cross-correlation vector includes updating the atleast one weight of the current filter to reduce a magnitude of thecross-correlation vector according to a recursive least squaresoptimization scheme.

In Example 169, the subject matter of Example 166 can optionally includewherein updating the at least one weight of the current filter to reducea magnitude of the cross-correlation vector includes updating the atleast one weight of the current filter to reduce a magnitude of thecross-correlation vector according to a recursive least squares (RLS)dichotomous coordinate descent (DCD) optimization scheme.

In Example 170, the subject matter of Example 166 or 169 can optionallyinclude wherein updating the at least one weight of the current filterto reduce a magnitude of the cross-correlation vector includesexclusively inverting a single bit of the first weight to reduce amagnitude of the cross-correlation vector.

In Example 171, the subject matter of Example 170 can optionally includewherein updating the at least one weight of the current filter to reducea magnitude of the cross-correlation vector further includes evaluatingone or more candidate bit inversions of the first weight to identifywhich of the one or more candidate bit inversions is closest to apredefined numerical difference, and identifying the single bitaccording to which of the one or more candidate bit inversions isclosest to the predefined numerical difference.

In Example 172, the subject matter of Example 170 can optionally includewherein exclusively inverting the single bit of the first weight toreduce a magnitude of the cross-correlation vector includes invertingthe single bit of the first weight according to a dichotomous coordinatedescent optimization scheme.

In Example 173, the subject matter of Example 162 can optionally includewherein selecting between the first filter and the second filter toidentify the current filter to update and the fixed filter to holdconstant includes selecting the first filter as the current filter andthe second filter as the fixed filter, and wherein applying the fixedfilter to the one or more subsignals to obtain the decoupled inputsignal includes applying previous delay taps of the second filter toprevious delay taps of the one or more subsignals during a preprocessingstage that occurs before receiving a most recent delay tap of the one ormore subsignals, and after receiving the most recent delay tap of theone or more subsignals, applying a most recent delay tap of the secondfilter to the most recent delay tap of the one or more subsignals.

In Example 174, the subject matter of Example 173 can optionally furtherinclude performing the preprocessing stage during hidden clock cyclesthat occur before the most recent delay tap of the one or moresubsignals is obtained.

In Example 175, the subject matter of Example 162 can optionally includewherein selecting between the first filter and the second filter toidentify the current filter to update and the fixed filter to holdconstant includes selecting the second filter as the current filter andthe first filter as the fixed filter, and wherein applying the fixedfilter to the one or more subsignals to obtain the decoupled inputsignal includes exclusively applying the first filter to samples of theone or more subsignals corresponding to a single delay tap of the one ormore subsignals to obtain a first element of the decoupled input signal.

In Example 176, the subject matter of Example 175 can optionally includewherein the remaining elements of the decoupled input signal aretime-delayed weighted versions of the first element of the decoupledinput signal.

In Example 177, the subject matter of any one of Examples 152 to 172 canoptionally include wherein alternating between updating the first filterand updating the second filter includes selecting between the firstfilter and the second filter to identify a current filter to update anda fixed filter to hold constant, applying the fixed filter to the one ormore subsignals to obtain a decoupled input signal, determining across-correlation vector between the decoupled input signal and theclean signal and determining a correlation matrix of the decoupled inputsignal, and updating at least one weight of the current filter based onthe cross-correlation vector and the correlation matrix.

In Example 178, the subject matter of Example 177 can optionally includewherein determining the cross-correlation vector between the decoupledinput signal and the clean signal includes determining some elements ofthe cross-correlation vector during a first clock cycle with firstcalculation circuitry and determining other elements of thecross-correlation vector during a second clock cycle with the same firstcalculation circuitry, or determining some elements of the correlationmatrix during a third clock cycle with second calculation circuitry anddetermining other elements of the correlation matrix during a secondclock cycle with the same second calculation circuitry.

In Example 179, the subject matter of Example 177 can optionally includewherein selecting between the first filter and the second filter toidentify a current filter to update and a fixed filter to hold constantincludes selecting the first filter as the current filter and the secondfilter as the fixed filter, and wherein determining thecross-correlation vector between the decoupled input signal and theclean signal and determining the correlation matrix of the decoupledinput signal includes exclusively determining the upper-triangleelements of the correlation matrix.

In Example 180, the subject matter of Example 179 can optionally includewherein the correlation matrix is Hermitian matrix.

In Example 181, the subject matter of Example 177 can optionally includewherein selecting between the first filter and the second filter toidentify the current filter to update and the fixed filter to holdconstant includes selecting the second filter as the current filter andthe first filter as the fixed filter, and wherein determining thecross-correlation vector between the decoupled input signal and theclean signal and determining the correlation matrix of the decoupledinput signal includes exclusively determining the a single row of thecorrelation matrix.

In Example 182, the subject matter of Example 181 can optionally includewherein a plurality of rows including the single row of the correlationmatrix are statistically similar.

In Example 183, the subject matter of any one of Examples 152 to 182 canoptionally include wherein alternating between updating the first filterand updating the second filter includes using shared circuitry to updatethe first filter and re-using the same shared circuitry to update thesecond filter.

In Example 184, the subject matter of any one of Examples 152 to 182 canoptionally include wherein alternating between updating the first filterand updating the second filter includes using shared circuitry to updatethe first filter and re-using the same shared circuitry to update thesecond filter according to a pipeline clock schedule.

In Example 185, the subject matter of any one of Examples 152 to 182 canoptionally include wherein alternating between updating the first filterand updating the second filter includes updating the first filter at oneor more first times and updating the delay tap dimension filter at oneor more different second times.

Example 186 is a communication circuitry arrangement configured toperform the method of any one of Examples 152 to 185.

In Example 187, the subject matter of Example 186 can optionally beconfigured as a radio communication device.

Example 188 is a non-transitory computer readable medium storinginstructions that when executed by a controller of a radio communicationdevice direct the radio communication device to perform the method ofany one of Examples 152 to 185.

Example 189 is a communication circuit arrangement including a signalpath circuit configured to separately apply a kernel dimension filterand a delay tap dimension filter to an input signal for an amplifier toobtain an estimated interference signal, a cancelation circuitconfigured to subtract the estimated interference signal from a receivedsignal to obtain a clean signal, and a filter update circuit configuredto alternate between updating the kernel dimension filter and the delaytap dimension filter using the clean signal.

In Example 190, the subject matter of Example 189 can optionally beconfigured as a radio communication device and further including areceive chain, a radio antenna, and a transmit chain including theamplifier.

In Example 191, the subject matter of Example 190 can optionally includewherein the amplifier is configured to amplify the input signal and theradio antenna is configured to transmit the amplified input signal.

In Example 192, the subject matter of Example 190 or 191 can optionallyinclude wherein the receive chain is configured to receive the receivedsignal via the radio antenna, wherein the estimated interference signalapproximates leakage from the transmit chain to the receive chain.

In Example 193, the subject matter of Example 189 can optionally includewherein the filter update circuit is configured to alternate betweenupdating the kernel dimension filter and updating the delay tapdimension filter using the clean signal by updating the kernel dimensionfilter in real-time over a first plurality of digital time samples ofthe input signal and updating the delay tap dimension filter inreal-time over a second plurality of digital time samples of the inputsignal.

In Example 194, the subject matter of Example 189 can optionally includewherein the input signal includes a plurality of digital time samples,and wherein alternating between updating the kernel dimension filter andupdating the delay tap dimension filter using the clean signal includesupdating the kernel dimension filter or the delay tap dimension filterover each of the plurality of digital time samples.

In Example 195, the subject matter of any one of Examples 189 to 194 canoptionally further include a kernel generation circuit configured toprocess the input signal to derive a plurality of kernel signals fromthe input signal, each of the plurality of kernel signals approximatinga non-linear component of a response of the amplifier wherein the signalpath circuit is configured to separately apply the kernel dimensionfilter and the delay dimension filter to the input signal by separatelyapplying the kernel dimension filter and the delay tap dimension filterto the plurality of kernel signals to obtain the estimated interferencesignal.

In Example 196, the subject matter of Example 195 can optionally includewherein each of the plurality of kernel signals is composed of aplurality of delay taps, wherein each weight of the kernel dimensionfilter corresponds to a respective one of the plurality of kernelsignals and each weight of the delay tap dimension filter corresponds toa respective one of the plurality of delay taps.

In Example 197, the subject matter of Example 196 can optionally includewherein the signal path circuit and the filter update circuit areconfigured to support an adjustable number of kernel signals or anadjustable number of delay taps.

In Example 198, the subject matter of Example 196 can optionally includewherein the kernel dimension filter approximates the response of theamplifier over the plurality of kernel signals and the delay tapdimension filter approximates the response of the amplifier over theplurality of delay taps.

In Example 199, the subject matter of any one of Examples 189 to 198 canoptionally include wherein the kernel dimension filter and the delay tapdimension filter are vectors.

In Example 200, the subject matter of any one of Examples 189 to 199 canoptionally include wherein the filter update circuit is configured toalternate between updating the kernel dimension filter and updating thedelay tap dimension filter by updating the kernel dimension filter andthe delay tap dimension filter based on the input signal and the cleansignal.

In Example 201, the subject matter of any one of Examples 195 to 200 canoptionally include wherein the filter update circuit is configured toalternate between updating the kernel dimension filter and the delay tapdimension filter by selecting between the kernel dimension filter andthe delay tap dimension filter to identify a current filter to updateand a fixed filter to hold constant, applying the fixed filter to theplurality of kernel signals to obtain a decoupled input signal, andcomparing the decoupled input signal to the clean signal to identify atleast one weight of the current filter to update.

In Example 202, the subject matter of Example 201 can optionally includewherein the filter update circuit is configured to compare the decoupledinput signal to identify the at least one weight of the current filterto update by determining a cross-correlation vector between thedecoupled input signal and the clean signal, identifying a first weightof the current filter to update based on the cross-correlation vector,and exclusively updating the first weight of the current filter.

In Example 203, the subject matter of Example 202 can optionally includewherein the filter update circuit is configured to identify the firstweight of the current filter to update based on the cross-correlationvector by identifying a maximum-valued element of the cross-correlationvector, and identifying the weight of the current filter with acorresponding element index to the maximum-valued element of thecross-correlation vector as the first weight.

In Example 204, the subject matter of Example 203 can optionally includewherein the filter update circuit is configured to identify themaximum-valued element of the cross-correlation vector by identifying anelement of the cross-correlation vector with the largest real componentor the largest imaginary component as the maximum-valued element.

In Example 205, the subject matter of Example 201 can optionally includewherein the filter update circuit is configured to compare the decoupledinput signal to the clean signal to identify the at least one weight ofthe current filter to update by determining a cross-correlation vectorbetween the decoupled input signal and the clean signal, and updatingthe at least one weight of the current filter to reduce a magnitude ofthe cross-correlation vector.

In Example 206, the subject matter of Example 205 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector by updating the at least one weight of thecurrent filter to reduce a magnitude of the cross-correlation vectoraccording to a recursive least squares optimization scheme.

In Example 207, the subject matter of Example 205 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector by updating the at least one weight of thecurrent filter to reduce a magnitude of the cross-correlation vectoraccording to a recursive least squares (RLS) dichotomous coordinatedescent (DCD) optimization scheme.

In Example 208, the subject matter of Example 205 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector by updating the at least one weight of thecurrent filter to reduce a magnitude of the cross-correlation vectoraccording to a coordinate descent optimization scheme.

In Example 209, the subject matter of Example 205 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector by exclusively inverting a single bit of thefirst weight to reduce a magnitude of the cross-correlation vector.

In Example 210, the subject matter of Example 209 can optionally includewherein the filter update circuit is further configured to update the atleast one weight of the current filter to reduce the cross-correlationvector by evaluating one or more candidate bit inversions of the firstweight to identify which of the one or more candidate bit inversions isclosest to a predefined numerical difference, and identifying the singlebit according to which of the one or more candidate bit inversions isclosest to the predefined numerical difference.

In Example 211, the subject matter of Example 209 can optionally includewherein the filter update circuit is configured to exclusively invertthe single bit of the first weight to reduce the magnitude of thecross-correlation vector by inverting the single bit of the first weightaccording to a dichotomous coordinate descent optimization scheme.

In Example 212, the subject matter of Example 201 can optionally includewherein the filter update circuit is configured to select between thekernel dimension filter and the delay tap dimension filter to identifythe current filter to update and the fixed filter to hold constant byselecting the kernel dimension filter as the current filter and thedelay tap dimension filter as the fixed filter, and wherein the filterupdate circuit is configured to apply the fixed filter to the pluralityof kernel signals to obtain the decoupled input signal by applyingprevious delay taps of the delay tap dimension filter to previous delaytaps of the plurality of kernel signals during a preprocessing stagethat occurs before receiving a most recent delay tap of the plurality ofkernel signals, and after receiving the most recent delay tap of theplurality of kernel signals, applying a most recent delay tap of thedelay tap dimension filter to the most recent delay tap of the pluralityof kernel signals.

In Example 213, the subject matter of Example 212 can optionally includewherein the filter update circuit is configured to perform thepreprocessing stage during hidden clock cycles that occur before themost recent delay tap of the plurality of kernel signals is obtained.

In Example 214, the subject matter of Example 201 can optionally includewherein the filter update circuit is configured to select between thekernel dimension filter and the delay tap dimension filter to identifythe current filter to update and the fixed filter to hold constant byselecting the delay tap dimension filter as the current filter and thekernel dimension filter as the fixed filter, and wherein the filterupdate circuit is configured to apply the fixed filter to the pluralityof kernel signals to obtain the decoupled input signal by exclusivelyapplying the kernel dimension filter to samples of the plurality ofkernel signals corresponding to a single delay tap to obtain a firstelement of the decoupled input signal.

In Example 215, the subject matter of Example 214 can optionally includewherein the remaining elements of the decoupled input signal aretime-delayed weighted versions of the first element of the decoupledinput signal.

In Example 216, the subject matter of any one of Examples 192 to 215 canoptionally include wherein the filter update circuit is configured toalternate between updating the kernel dimension filter and updating thedelay tap dimension filter by selecting between the kernel dimensionfilter and the delay tap dimension filter to identify a current filterto update and a fixed filter to hold constant, applying the fixed filterto the plurality of kernel signals to obtain a decoupled input signal,determining a cross-correlation vector between the decoupled inputsignal and the clean signal and determining a correlation matrix of thedecoupled input signal, and updating at least one weight of the currentfilter based on the cross-correlation vector and the correlation matrix.

In Example 217, the subject matter of Example 216 can optionally includewherein the filter update circuit is configured to determine thecross-correlation vector between the decoupled input signal and theclean signal by determining some elements of the cross-correlationvector during a first clock cycle with first calculation circuitry anddetermining other elements of the cross-correlation vector during asecond clock cycle with the same first calculation circuitry, ordetermining some elements of the correlation matrix during a third clockcycle with second calculation circuitry and determining other elementsof the correlation matrix during a second clock cycle with the samesecond calculation circuitry.

In Example 218, the subject matter of Example 216 can optionally includewherein the filter update circuit is configured to select between thekernel dimension filter and the delay tap dimension filter to identifythe current filter to update and the fixed filter to hold constant byselecting the kernel dimension filter as the current filter and thedelay tap dimension filter as the fixed filter, and wherein the filterupdate circuit is configured to determine the cross-correlation vectorbetween the decoupled input signal and the clean signal and determiningthe correlation matrix of the decoupled input signal by exclusivelydetermining the upper-triangle elements of the correlation matrix.

In Example 219, the subject matter of Example 218 can optionally includewherein the correlation matrix is a Hermitian matrix.

In Example 220, the subject matter of Example 216 can optionally includewherein the filter update circuit is configured to select between thekernel dimension filter and the delay tap dimension filter to identifythe current filter to update and the fixed filter to hold constant byselecting the delay tap dimension filter as the current filter and thekernel dimension filter as the fixed filter, and wherein the filterupdate circuit is configured to determine the cross-correlation vectorbetween the decoupled input signal and the clean signal and determiningthe correlation matrix of the decoupled input signal by exclusivelydetermining a single row of the correlation matrix.

In Example 221, the subject matter of Example 220 can optionally includewherein a plurality of rows including the single row of the correlationmatrix are statistically similar.

In Example 222, the subject matter of any one of Examples 189 to 221 canoptionally include wherein the filter update circuit is configured toalternate between updating the kernel dimension filter and updating thedelay tap dimension filter by using shared circuitry to update thekernel dimension filter and re-using the same shared circuitry to updatethe delay tap dimension filter.

In Example 223, the subject matter of any one of Examples 189 to 221 canoptionally include wherein the filter update circuit is configured toalternate between updating the kernel dimension filter and updating thedelay tap dimension filter by using shared circuitry to update thekernel dimension filter and re-using the same shared circuitry to updatethe delay tap dimension filter according to a pipeline clock schedule.

In Example 224, the subject matter of Example 223 can optionally includewherein the filter update circuit is configured to alternate betweenupdating the kernel dimension filter and updating the delay tapdimension filter by updating the kernel dimension filter at one or morefirst times and updating the delay tap dimension at one or moredifferent second times.

Example 225 is a communication circuit arrangement including a subsignalgeneration circuit configured to obtain one or more subsignals from aninput signal for an amplifier, each of the one or more subsignalsrepresenting a non-linear component of an amplifier response andcomposed of a plurality of delay taps, a signal path circuit configuredto separately apply a first filter and a second filter to the one ormore subsignals to obtain an estimated interference signal, wherein thefirst filter approximates the amplifier response over the one or moresubsignals and the second filter approximates the amplifier responseover the plurality of delay taps, a cancelation circuit configured tosubtract the estimated interference signal from the received signal toobtain a clean signal, and a filter update circuit configured toalternate between updating the first filter and alternating the secondfilter using the clean signal.

In Example 226, the subject matter of Example 225 can optionally beconfigured as a radio communication device and further including areceive chain, a radio antenna, and a transmit chain including theamplifier.

In Example 227, the subject matter of Example 226 can optionally includewherein the amplifier is configured to amplify the input signal and theradio antenna is configured to transmit the amplified input signal.

In Example 228, the subject matter of Example 226 or 227 can optionallyinclude wherein the receive chain is configured to receive the receivedsignal via the radio antenna, wherein the estimated interference signalapproximates leakage from the transmit chain to the receive chain.

In Example 229, the subject matter of any one of Examples 225 to 228 canoptionally include wherein the filter update circuit is configured toalternate between updating the first filter and the second filter byupdating the first filter in real-time over a first plurality of digitaltime samples of the input signal and updating the second filter inreal-time over a second plurality of digital time samples of the inputsignal

In Example 230, the subject matter of any one of Examples 225 to 228 canoptionally include wherein the input signal includes a plurality ofdigital time samples, and wherein alternating between updating the firstfilter and updating the second filter using the clean signal includesupdating the first filter or the second filter over each of theplurality of digital time samples.

In Example 231, the subject matter of any one of Examples 225 to 228 canoptionally include wherein each of the one or more subsignals correspondto a kernel of the amplifier.

In Example 232, the subject matter of any one of Examples 225 to 231 canoptionally include wherein the first filter and the second filter arevectors.

In Example 233, the subject matter of any one of Examples 225 to 232 canoptionally include wherein each of weight of the first filtercorresponds to a respective one of the one or more subsignals and eachweight of the second filter corresponds to a respective delay tap of theplurality of delay taps.

In Example 234, the subject matter of any one of Examples 225 to 233 canoptionally include wherein the signal path circuit and the filter updatecircuit are configured to support an adjustable number of subsignals oran adjustable number of delay taps.

In Example 235, the subject matter of any one of Examples 225 to 234 canoptionally include wherein the filter update circuit is configured toalternate between updating the first filter and updating the secondfilter by updating the first filter and the second filter based on theone or more subsignals and the clean signal.

In Example 236, the subject matter of any one of Examples 225 to 234 canoptionally include wherein the filter update circuit is configured toalternate between updating the first filter and updating the secondfilter by selecting between the first filter and the second filter toidentify a current filter to update and a fixed filter to hold constant,applying the fixed filter to the one or more subsignals to obtain adecoupled input signal, and comparing the decoupled input signal to theclean signal to identify at least one weight of the current filter toupdate.

In Example 237, the subject matter of Example 236 can optionally includewherein the filter update circuit is configured to compare the decoupledinput signal to the clean signal to identify the at least one weight ofthe current filter to update by determining a cross-correlation vectorbetween the decoupled input signal and the clean signal, identifying afirst weight of the current filter to update based on thecross-correlation vector, and exclusively updating the first weight ofthe current filter.

In Example 238, the subject matter of Example 237 can optionally includewherein the filter update circuit is configured to identify the firstweight of the current filter to update based on the cross-correlationvector by identifying a maximum-valued element of the cross-correlationvector, and identifying the weight of the current filter with acorresponding element index to the maximum-valued element of thecross-correlation vector as the first weight.

In Example 239, the subject matter of Example 238 can optionally includewherein the filter update circuit is configured to identify themaximum-valued element of the cross-correlation vector by identifyingthe element of the cross-correlation vector with the largest realcomponent or the largest imaginary component as the maximum-valuedelement.

In Example 240, the subject matter of Example 236 can optionally includewherein the filter update circuit is configured to compare the decoupledinput signal to the clean signal to identify the at least one weight ofthe current filter to update by determining a cross-correlation vectorbetween the decoupled input signal and the clean signal, and updatingthe at least one weight of the current filter to reduce a magnitude ofthe cross-correlation vector.

In Example 241, the subject matter of Example 240 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector by updating the at least one weight of thecurrent filter to reduce a magnitude of the cross-correlation vectoraccording to a coordinate descent optimization scheme.

In Example 242, the subject matter of Example 240 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector by updating the at least one weight of thecurrent filter to reduce a magnitude of the cross-correlation vectoraccording to a recursive least squares optimization scheme.

In Example 243, the subject matter of Example 240 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector by updating the at least one weight of thecurrent filter to reduce a magnitude of the cross-correlation vectoraccording to a recursive least squares (RLS) dichotomous coordinatedescent (DCD) optimization scheme.

In Example 244, the subject matter of Example 240 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector by exclusively inverting a single bit of thefirst weight to reduce a magnitude of the cross-correlation vector.

In Example 245, the subject matter of Example 244 can optionally includewherein the filter update circuit is configured to update the at leastone weight of the current filter to reduce a magnitude of thecross-correlation vector further by evaluating one or more candidate bitinversions of the first weight to identify which of the one or morecandidate bit inversions is closest to a predefined numericaldifference, and identifying the single bit according to which of the oneor more candidate bit inversions is closest to the predefined numericaldifference.

In Example 246, the subject matter of Example 244 can optionally includewherein the filter update circuit is configured to exclusively invertthe single bit of the first weight to reduce a magnitude of thecross-correlation vector by inverting the single bit of the first weightaccording to a dichotomous coordinate descent optimization scheme.

In Example 247, the subject matter of Example 236 can optionally includewherein the filter update circuit is configured to select between thefirst filter and the second filter to identify the current filter toupdate and the fixed filter to hold constant by selecting the firstfilter as the current filter and the second filter as the fixed filter,and wherein the filter update circuit is configured to apply the fixedfilter to the one or more subsignals to obtain the decoupled inputsignal by applying previous delay taps of the second filter to previousdelay taps of the one or more subsignals during a preprocessing stagethat occurs before receiving a most recent delay tap of the one or moresubsignals, and after receiving the most recent delay tap of the one ormore subsignals, applying a most recent delay tap of the second filterto the most recent delay tap of the one or more subsignals.

In Example 248, the subject matter of Example 247 can optionally includewherein the filter update circuit is configured to perform thepreprocessing stage during hidden clock cycles that occur before themost recent delay tap of the one or more subsignals is obtained.

In Example 249, the subject matter of Example 236 can optionally includewherein the filter update circuit is configured to select between thefirst filter and the second filter to identify the current filter toupdate and the fixed filter to hold constant by selecting the secondfilter as the current filter and the first filter as the fixed filter,and wherein applying the fixed filter to the one or more subsignals toobtain the decoupled input signal by exclusively applying the firstfilter to samples of the one or more subsignals corresponding to asingle delay tap of the one or more subsignals to obtain a first elementof the decoupled input signal.

In Example 250, the subject matter of Example 249 can optionally includewherein the remaining elements of the decoupled input signal aretime-delayed weighted versions of the first element of the decoupledinput signal.

In Example 251, the subject matter of any one of Examples 225 to 246 canoptionally include wherein the filter update circuit is configured toalternate between updating the first filter and updating the secondfilter by selecting between the first filter and the second filter toidentify a current filter to update and a fixed filter to hold constant,applying the fixed filter to the one or more subsignals to obtain adecoupled input signal, determining a cross-correlation vector betweenthe decoupled input signal and the clean signal and determining acorrelation matrix of the decoupled input signal, and updating at leastone weight of the current filter based on the cross-correlation vectorand the correlation matrix.

In Example 252, the subject matter of Example 251 can optionally includewherein the filter update circuit is configured to determine thecross-correlation vector between the decoupled input signal and theclean signal by determining some elements of the cross-correlationvector during a first clock cycle with first calculation circuitry anddetermining other elements of the cross-correlation vector during asecond clock cycle with the same first calculation circuitry, ordetermining some elements of the correlation matrix during a third clockcycle with second calculation circuitry and determining other elementsof the correlation matrix during a second clock cycle with the samesecond calculation circuitry.

In Example 253, the subject matter of Example 251 can optionally includewherein the filter update circuit is configured to select between thefirst filter and the second filter to identify a current filter toupdate and a fixed filter to hold constant by selecting the first filteras the current filter and the second filter as the fixed filter, andwherein the filter update circuit is configured to determine thecross-correlation vector between the decoupled input signal and theclean signal and determining the correlation matrix of the decoupledinput signal by exclusively determining the upper-triangle elements ofthe correlation matrix.

In Example 254, the subject matter of Example 253 can optionally includewherein the correlation matrix is Hermitian matrix.

In Example 255, the subject matter of Example 251 can optionally includewherein the filter update circuit is configured to select between thefirst filter and the second filter to identify the current filter toupdate and the fixed filter to hold constant by selecting the secondfilter as the current filter and the first filter as the fixed filter,and wherein the filter update circuit is configured to determine thecross-correlation vector between the decoupled input signal and theclean signal and determining the correlation matrix of the decoupledinput signal by exclusively determining the a single row of thecorrelation matrix.

In Example 256, the subject matter of Example 255 can optionally includewherein a plurality of rows including the single row of the correlationmatrix are statistically similar.

In Example 257, the subject matter of any one of Examples 225 to 256 canoptionally include wherein the filter update circuit is configured toalternate between updating the first filter and updating the secondfilter by using shared circuitry to update the first filter and re-usingthe same shared circuitry to update the second filter.

In Example 258, the subject matter of any one of Examples 225 to 256 canoptionally include wherein the filter update circuit is configured toalternate between updating the first filter and updating the secondfilter by using shared circuitry to update the first filter and re-usingthe same shared circuitry to update the second filter according to apipeline clock schedule.

In Example 259, the subject matter of any one of Examples 225 to 256 canoptionally include wherein the filter update circuit is configured toalternate between updating the first filter and updating the secondfilter by updating the first filter at one or more first times andupdating the delay tap dimension filter at one or more different secondtimes.

All acronyms defined in the above description additionally hold in allclaims included herein.

While the invention has been particularly shown and described withreference to specific embodiments, it should be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention asdefined by the appended claims. The scope of the invention is thusindicated by the appended claims and all changes which come within themeaning and range of equivalency of the claims are therefore intended tobe embraced.

1. A communication circuit comprising: a signal path circuit configuredto estimate, using a first kernel dimension filter and a first delay tapdimension filter, a first interference signal from a first amplifier,and estimate, using a second kernel dimension filter and a second delaytap dimension filter, a second interference signal from a secondamplifier; and a cancellation circuit configured to subtract acombination of the estimated first interference signal and the estimatedsecond interference signal from a received signal to obtain a filteredreceived signal, wherein the combination of the estimated firstinterference signal and the estimated second interference signal isrepresentative of signal interference caused by signal leakage into areceive path of the received signal.
 2. The communication circuit ofclaim 1, further comprising: one or more receive chains; a firsttransmit chain comprising the first amplifier; a second transmit chaincomprising the second amplifier; and one or more antennas coupled to theone or more receive chains and the first transmit chain.
 3. Thecommunication circuit of claim 1, wherein the signal path circuit isfurther configured to: obtain the estimated first interference signal byapplying a first filter circuit that comprises the first kerneldimension filter and the first delay tap dimension filter to an inputsignal of the first amplifier; and obtain the estimated secondinterference signal by applying a second filter circuit that comprisesthe second kernel dimension filter and the second delay tap dimensionfilter to an input signal of the second amplifier.
 4. The communicationcircuit of claim 3, further comprising: a first kernel generationcircuit configured to process the input signal of the first amplifier toderive a corresponding first plurality of kernel signals, each of thefirst plurality of kernel signals approximating a non-linear componentof a leakage path of the first amplifier, and a second kernel generationcircuit configured to process the input signal of the second amplifierto derive a corresponding second plurality of kernel signals, each ofthe second plurality of kernel signals approximating a non-linearcomponent of a leakage path of the second amplifier, wherein applyingthe first filter circuit to the input signal of the first amplifiercomprises applying the first kernel dimension filter to the firstplurality of kernel signals, and wherein applying the second filtercircuit to the input signal of the second amplifier comprises applyingthe second kernel dimension filter to the second plurality of kernelsignals.
 5. The communication circuit of claim 1, further comprising:one or more filter adaptation circuits configured to: alternate betweena kernel update phase and a delay update phase, update the first kerneldimension filter and the second kernel dimension filter during thekernel update phase, and update the first delay tap dimension filter andthe second delay tap dimension filter during the delay update phase. 6.The communication circuit of claim 2, wherein: the first amplifier isconfigured to amplify a first input signal to form a first amplifiedsignal; the second amplifier is configured to amplify a second inputsignal to form a second amplified signal; the one or more antennas areconfigured to transmit the first amplified signal and the secondamplified signal; the estimated first interference signal is based onthe first input signal; and the estimated second interference signal isbased on the second input signal.
 7. The communication circuit of claim2, wherein: the receive path comprises a first receive chain of the oneor more receive chains; the first receive chain is configured to receivethe received signal via the one or more antennas; and the combination ofthe estimated first interference signal and the estimated secondinterference signal is an approximation of signal leakage from the firsttransmit chain and the second transmit chain into the first receivechain.
 8. The communication circuit of claim 1, wherein the signal pathcircuit comprises: a combiner configured to combine the estimated firstinterference signal with the estimated second interference signal toobtain the combination of the estimated first interference signal andthe estimated second interference signal.
 9. A wireless communicationdevice comprising: one or more receive chains; a first transmit chaincomprising a first amplifier; a second transmit chain comprising asecond amplifier; one or more antennas coupled to the one or morereceive chains and the first transmit chain; and cancellation circuitryconfigured to estimate, using a first kernel dimension filter and afirst delay tap dimension filter, a first interference signal from afirst amplifier, estimate, using a second kernel dimension filter and asecond delay tap dimension filter, a second interference signal from asecond amplifier, and subtract a combination of the estimated firstinterference signal and the estimated second interference signal from areceived signal to obtain a filtered received signal, wherein thecombination of the estimated first interference signal and the estimatedsecond interference signal is representative of signal interferenceassociated with the first amplifier and the second amplifier andaffecting the received signal.
 10. The wireless communication device ofclaim 9, wherein the cancellation circuitry comprises one or more filteradaptation circuits configured to: alternate between a kernel updatephase and a delay update phase; update the first kernel dimension filterand the second kernel dimension filter during the kernel update phase;and update the first delay tap dimension filter and the second delay tapdimension filter during the delay update phase.
 11. The wirelesscommunication device of claim 9, wherein the cancellation circuitry isfurther configured to: obtain the estimated first interference signal byapplying a first filter circuit that comprises the first kerneldimension filter and the first delay tap dimension filter to an inputsignal of the first amplifier; and obtain the estimated secondinterference signal by applying a second filter circuit that comprisesthe second kernel dimension filter and the second delay tap dimensionfilter to an input signal of the second amplifier.
 12. The wirelesscommunication device of claim 11, wherein the cancellation circuitrycomprises: a first kernel generation circuit configured to process theinput signal of the first amplifier to derive a corresponding firstplurality of kernel signals, each of the first plurality of kernelsignals approximating a non-linear component of a leakage path of thefirst amplifier; and a second kernel generation circuit configured toprocess the input signal of the second amplifier to derive acorresponding second plurality of kernel signals, each of the secondplurality of kernel signals approximating a non-linear component of aleakage path of the second amplifier; wherein applying the first filtercircuit to the input signal of the first amplifier comprises applyingthe first kernel dimension filter to the first plurality of kernelsignals, and wherein applying the second filter circuit to the inputsignal of the second amplifier comprises applying the second kerneldimension filter to the second plurality of kernel signals.
 13. Thewireless communication device of claim 9, wherein: the first amplifieris configured to amplify a first input signal to form a first amplifiedsignal; the second amplifier is configured to amplify a second inputsignal to form a second amplified signal; the one or more antennas areconfigured to transmit the first amplified signal and the secondamplified signal; the estimated first interference signal is based onthe first input signal; and the estimated second interference signal isbased on the second input signal.
 14. The wireless communication deviceof claim 9, wherein: wherein a first receive chain of the one or morereceive chains is configured to receive the received signal via the oneor more antennas; and the combination of the estimated firstinterference signal and the estimated second interference signal is anapproximation of signal leakage from the first transmit chain and thesecond transmit chain into the first receive chain.
 15. A method ofperforming interference cancellation, the method comprising: estimating,using a first kernel dimension filter and a first delay tap dimensionfilter, a first interference signal from a first amplifier; estimating,using a second kernel dimension filter and a second delay tap dimensionfilter, a second interference signal from a second amplifier; andsubtracting a combination of the first interference signal and thesecond interference signal from a received signal to obtain a filteredreceived signal, wherein the combination of the first interferencesignal and the second interference signal is representative of signalinterference affecting the received signal.
 16. The method of claim 15,further comprising: updating the first kernel dimension filter and thesecond kernel dimension filter during a kernel update phase; updatingthe first delay tap dimension filter and the second delay tap dimensionfilter during a delay update phase; and alternating between the kernelupdate phase and the delay update phase.
 17. The method of claim 15,wherein: estimating the first interference signal comprises applying afirst filter circuit that comprises the first kernel dimension filterand the first delay tap dimension filter to an input signal of the firstamplifier; and estimating the second interference signal comprisesapplying a second filter circuit that comprises the second kerneldimension filter and the second delay tap dimension filter to an inputsignal of the second amplifier.
 18. The method of claim 17, furthercomprising: deriving a first plurality of kernel signals by processingthe input signal of the first amplifier, each of the first plurality ofkernel signals approximating a non-linear component of a leakage path ofthe first amplifier; and deriving a second plurality of kernel signalsby processing the input signal of the second amplifier, each of thesecond plurality of kernel signals approximating a non-linear componentof a leakage path of the second amplifier; wherein applying the firstfilter circuit to the input signal of the first amplifier comprisesapplying the first kernel dimension filter to the first plurality ofkernel signals, and wherein applying the second filter circuit to theinput signal of the second amplifier comprises applying the secondkernel dimension filter to the second plurality of kernel signals. 19.The method of claim 15, further comprising: generating a first amplifiedsignal by amplifying a first input signal via the first amplifier;generating a second amplified signal by amplify a second input signalvia the second amplifier; transmitting the first amplified signal andthe second amplified signal via one or more antennas; wherein theestimated first interference signal is based on the first input signal;and wherein the estimated second interference signal is based on thesecond input signal.
 20. The method of claim 15, wherein: the firstamplifier is comprised in a first transmit path; the second amplifier iscomprised in a second transmit path; the received signal is received ina receive chain; and the combination of the estimated first interferencesignal and the estimated second interference signal is an approximationof signal leakage from the first transmit chain and the second transmitchain into the receive chain.